From: Andre Przywara <andre.przywara@linaro.org>
To: Julien Grall <julien.grall@arm.com>,
Stefano Stabellini <sstabellini@kernel.org>
Cc: xen-devel@lists.xenproject.org,
Andrew Cooper <andrew.cooper3@citrix.com>
Subject: Re: [PATCH v2 40/45] ARM: new VGIC: vgic-init: register VGIC
Date: Tue, 20 Mar 2018 17:11:51 +0000 [thread overview]
Message-ID: <32f47f2e-181e-f1e4-3eac-bfafd5a16d11@linaro.org> (raw)
In-Reply-To: <1bf5c369-5f80-3020-31bc-3871869220f2@arm.com>
Hi,
On 20/03/18 01:17, Julien Grall wrote:
> Hi Andre,
>
> On 03/15/2018 08:30 PM, Andre Przywara wrote:
>> diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c
>> index 002fec57e6..4b9664f313 100644
>> --- a/xen/arch/arm/vgic/vgic.c
>> +++ b/xen/arch/arm/vgic/vgic.c
>> @@ -946,6 +946,28 @@ void vgic_sync_hardware_irq(struct domain *d,
>> spin_unlock_irqrestore(&desc->lock, flags);
>> }
>> +unsigned int vgic_max_vcpus(const struct domain *d)
>> +{
>> + unsigned int vgic_vcpu_limit;
>> +
>> + switch ( d->arch.vgic.version )
>> + {
>> +#ifdef CONFIG_HAS_GICV3
>> + case GIC_V3:
>> + vgic_vcpu_limit = VGIC_V3_MAX_CPUS;
>> + break;
>> +#endif
>
> It is a bit strange that you handle GICV3 here but don't in
> domain_vgic_register.
Fair enough.
>> + case GIC_V2:
>> + vgic_vcpu_limit = VGIC_V2_MAX_CPUS;
>> + break;
>> + default:
>> + vgic_vcpu_limit = MAX_VIRT_CPUS;
>
> I feel this is a bit odd. We only support GICv2 and GICv3 and the enum
> has two values. Likely GCC will complain if CONFIG_HAS_GICV3 is set
> because default label is not used.
AFAICT (and have tested) at least my GCC never complains about
"default:", even if every enum member has already been used. I think
it's good style to catch those cases should the enum get extended for
some reason.
Plus we have this already in arch_domain_create() (in switch
get_hw_version()).
> Lastly, I can't see how you handle the corner case mentioned in the
> current vGIC:
>
> /*
> * Since evtchn_init would call domain_max_vcpus for poll_mask
> * allocation when the vgic_ops haven't been initialised yet,
> * we return MAX_VIRT_CPUS if d->arch.vgic.handler is null.
> */
Do we need this still with Andrew's latest patch?
> The comment in the code would also be very useful as the reason to call
> vgic_max_vcpus before the full initialization is not that straightforward.
Otherwise this smells like we need to have enum gic_version extended, to
reserve the 0 case? enum gic_version {GIC_INVALID, GIC_V2, GIC_V3};?
That should cover the not-yet-initialised case, shouldn't it?
Cheers,
Andre.
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
next prev parent reply other threads:[~2018-03-20 17:12 UTC|newest]
Thread overview: 106+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-15 20:30 [PATCH v2 00/45] New VGIC(-v2) implementation Andre Przywara
2018-03-15 20:30 ` [PATCH v2 01/45] ARM: VGIC: rename gic_event_needs_delivery() Andre Przywara
2018-03-16 10:58 ` Julien Grall
2018-03-16 21:21 ` Stefano Stabellini
2018-03-15 20:30 ` [PATCH v2 02/45] ARM: Implement vcpu_kick() Andre Przywara
2018-03-16 10:59 ` Julien Grall
2018-03-16 21:23 ` Stefano Stabellini
2018-03-20 10:35 ` Jan Beulich
2018-03-21 4:10 ` Julien Grall
2018-03-21 7:40 ` Jan Beulich
2018-03-15 20:30 ` [PATCH v2 03/45] xen/arm: gic: Fix indentation in gic_update_one_lr Andre Przywara
2018-03-15 20:30 ` [PATCH v2 04/45] xen/arm: vgic: Override the group in lr everytime Andre Przywara
2018-03-16 21:25 ` Stefano Stabellini
2018-03-15 20:30 ` [PATCH v2 05/45] xen/arm: gic: Use bool instead of uint8_t for the hw_status in gic_lr Andre Przywara
2018-03-16 21:25 ` Stefano Stabellini
2018-03-15 20:30 ` [PATCH v2 06/45] xen/arm: gic: Split the field state in gic_lr in 2 fields active and pending Andre Przywara
2018-03-16 21:34 ` Stefano Stabellini
2018-03-16 22:14 ` Julien Grall
2018-03-16 22:52 ` Stefano Stabellini
2018-03-19 9:10 ` Andre Przywara
2018-03-15 20:30 ` [PATCH v2 07/45] xen/arm: GIC: Only set pirq in the LR when hw_status is set Andre Przywara
2018-03-16 21:38 ` Stefano Stabellini
2018-03-15 20:30 ` [PATCH v2 08/45] ARM: GIC: extend LR read/write functions to cover EOI and source Andre Przywara
2018-03-16 21:43 ` Stefano Stabellini
2018-03-15 20:30 ` [PATCH v2 09/45] ARM: GIC: Allow tweaking the active and pending state of an IRQ Andre Przywara
2018-03-16 16:05 ` Andre Przywara
2018-03-19 9:30 ` Julien Grall
2018-03-19 17:54 ` Andre Przywara
2018-03-20 0:57 ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 10/45] ARM: GIC: Allow reading pending state of a hardware IRQ Andre Przywara
2018-03-19 10:04 ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 11/45] ARM: timer: Handle level triggered IRQs correctly Andre Przywara
2018-03-19 10:07 ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 12/45] ARM: evtchn: " Andre Przywara
2018-03-19 10:54 ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 13/45] ARM: vPL011: Use the VGIC's level triggered IRQs handling if available Andre Przywara
2018-03-19 10:59 ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 14/45] ARM: new VGIC: Add data structure definitions Andre Przywara
2018-03-19 11:01 ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 15/45] ARM: new VGIC: Add acccessor to new struct vgic_irq instance Andre Przywara
2018-03-19 11:04 ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 16/45] ARM: new VGIC: Implement virtual IRQ injection Andre Przywara
2018-03-19 12:48 ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 17/45] Add list_sort() routine from Linux Andre Przywara
2018-03-16 10:47 ` Jan Beulich
2018-03-15 20:30 ` [PATCH v2 18/45] ARM: new VGIC: Add IRQ sorting Andre Przywara
2018-03-19 12:51 ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 19/45] ARM: new VGIC: Add IRQ sync/flush framework Andre Przywara
2018-03-19 14:17 ` Julien Grall
2018-03-19 17:32 ` Andre Przywara
2018-03-15 20:30 ` [PATCH v2 20/45] ARM: new VGIC: Add GICv2 world switch backend Andre Przywara
2018-03-19 14:36 ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 21/45] ARM: new VGIC: Implement vgic_vcpu_pending_irq Andre Przywara
2018-03-19 7:55 ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 22/45] ARM: new VGIC: Add MMIO handling framework Andre Przywara
2018-03-19 7:59 ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 23/45] ARM: new VGIC: Add GICv2 " Andre Przywara
2018-03-15 20:30 ` [PATCH v2 24/45] ARM: new VGIC: Add CTLR, TYPER and IIDR handlers Andre Przywara
2018-03-19 8:13 ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 25/45] ARM: new VGIC: Add ENABLE registers handlers Andre Przywara
2018-03-19 8:22 ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 26/45] ARM: new VGIC: Add PENDING " Andre Przywara
2018-03-19 8:25 ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 27/45] ARM: new VGIC: Add ACTIVE " Andre Przywara
2018-03-19 8:27 ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 28/45] ARM: new VGIC: Add PRIORITY " Andre Przywara
2018-03-19 9:40 ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 29/45] ARM: new VGIC: Add CONFIG " Andre Przywara
2018-03-15 20:30 ` [PATCH v2 30/45] ARM: new VGIC: Add TARGET " Andre Przywara
2018-03-19 9:44 ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 31/45] ARM: new VGIC: Add SGIR register handler Andre Przywara
2018-03-19 9:47 ` Julien Grall
2018-03-19 16:21 ` Andre Przywara
2018-03-15 20:30 ` [PATCH v2 32/45] ARM: new VGIC: Add SGIPENDR register handlers Andre Przywara
2018-03-15 20:30 ` [PATCH v2 33/45] ARM: new VGIC: Handle hardware mapped IRQs Andre Przywara
2018-03-15 20:30 ` [PATCH v2 34/45] ARM: new VGIC: Add event channel IRQ handling Andre Przywara
2018-03-15 20:30 ` [PATCH v2 35/45] ARM: new VGIC: Handle virtual IRQ allocation/reservation Andre Przywara
2018-03-15 20:30 ` [PATCH v2 36/45] ARM: new VGIC: Dump virtual IRQ info Andre Przywara
2018-03-15 20:30 ` [PATCH v2 37/45] ARM: new VGIC: Provide system register emulation stub Andre Przywara
2018-03-15 20:30 ` [PATCH v2 38/45] ARM: new VGIC: Implement arch_move_irqs() Andre Przywara
2018-03-19 9:53 ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 39/45] ARM: new VGIC: Add preliminary stub implementation Andre Przywara
2018-03-19 9:54 ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 40/45] ARM: new VGIC: vgic-init: register VGIC Andre Przywara
2018-03-20 1:17 ` Julien Grall
2018-03-20 17:11 ` Andre Przywara [this message]
2018-03-21 4:29 ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 41/45] ARM: new VGIC: Add vgic_v2_enable Andre Przywara
2018-03-19 9:57 ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 42/45] ARM: new VGIC: vgic-init: implement vgic_init Andre Przywara
2018-03-20 3:02 ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 43/45] ARM: new VGIC: vgic-init: implement map_resources Andre Przywara
2018-03-20 3:10 ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 44/45] ARM: new VGIC: Allocate two pages for struct vcpu Andre Przywara
2018-03-19 10:00 ` Julien Grall
2018-03-19 10:04 ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 45/45] ARM: VGIC: wire new VGIC(-v2) files into Xen build system Andre Przywara
2018-03-16 10:48 ` Jan Beulich
2018-03-16 11:10 ` Andre Przywara
2018-03-16 11:32 ` Jan Beulich
2018-03-16 15:13 ` Andre Przywara
2018-03-16 15:34 ` Jan Beulich
2018-03-20 3:13 ` Julien Grall
2018-03-20 15:57 ` Andre Przywara
2018-03-20 8:30 ` [PATCH v2 00/45] New VGIC(-v2) implementation Julien Grall
2018-03-20 11:20 ` Andre Przywara
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=32f47f2e-181e-f1e4-3eac-bfafd5a16d11@linaro.org \
--to=andre.przywara@linaro.org \
--cc=andrew.cooper3@citrix.com \
--cc=julien.grall@arm.com \
--cc=sstabellini@kernel.org \
--cc=xen-devel@lists.xenproject.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).