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Mon, 14 Sep 2026 06:27:21 -0700 (PDT) Message-ID: <45f6e417-ea0e-470c-bfae-e163a65b48d0@suse.com> Date: Mon, 14 Sep 2026 15:27:07 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 31/39] xen/riscv: implement APLIC-hart sync barrier for vCPU migration To: Oleksii Kurochko Cc: Romain Caritey , Baptiste Le Duc , Zheng Zhang , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , xen-devel@lists.xenproject.org References: <3d953b6e7f221f4cf4143454076466fab38b6236.1787838835.git.oleksii.kurochko@gmail.com> Content-Language: en-US From: Jan Beulich In-Reply-To: <3d953b6e7f221f4cf4143454076466fab38b6236.1787838835.git.oleksii.kurochko@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-16d1c6/1789392441-F74C977B-09ED7B40/0/0 X-purgate-type: clean X-purgate-size: 1492 On 27.08.2026 17:21, Oleksii Kurochko wrote: > During migration of a virtual hart to a different guest interrupt file, > straggler MSIs from the APLIC could arrive at the old interrupt file > after the switch. > > genmsi is used despite not supporting guest interrupt files because the > AIA spec guarantees that all MSIs previously sent from the APLIC to the > same hart are visible at the hart's IMSIC before the extempore MSI from > genmsi becomes visible. Hmm. As indicated, I'm learning RISC-V as I'm reviewing patches. This paragraph, if left as is, would make sure I simply can't ack the patch. I just don't understand what is being talked about. I can guess parts, but for example I don't know what "genmsi" is. > @@ -205,6 +207,30 @@ void aplic_hw_write_reg(unsigned int offset, uint32_t value) > spin_unlock_irqrestore(&aplic.lock, flags); > } > > +/* > + * As needed, synchronize with all IOMMUs and APLICs to ensure that no > + * straggler MSIs will arrive at the old interrupt file after this step. > + */ > +void aplic_genmsi_barrier(void) > +{ > + const struct imsic_config *imsic = imsic_get_config(); > + unsigned int cpu = smp_processor_id(); > + unsigned long flags; > + uint32_t val; > + > + val = MASK_INSR(aplic_hart_field(cpu), APLIC_TARGET_HART_IDX) | > + (imsic->sync_id & APLIC_TARGET_EIID); Along the lines of a question on an earlier patch: What if this ANDing actually chops off bits? Jan