From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Jan Beulich" Subject: Re: [help] rsp in case of interrupt/exception in ring0 Date: Wed, 24 Feb 2010 08:35:31 +0000 Message-ID: <4B84F2E30200007800030ECC@vpn.id2.novell.com> References: <20100223193957.33c3e13e@mantra.us.oracle.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: <20100223193957.33c3e13e@mantra.us.oracle.com> Content-Disposition: inline List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: "Xen-devel@lists.xensource.com" , Mukesh Rathor List-Id: xen-devel@lists.xenproject.org >>> Mukesh Rathor 24.02.10 04:39 >>> >When a cpu is in hyp code and int/exception comes in, how/where is rsp=20 >saved? According to intel manual if there's no ring transition, then >the cpu doesn't save ss/rsp.=20 As you're apparently talking about x86-64, you probably simply read the wrong (32-bit) part of the manual. On 64-bits, ss:rsp are always getting saved, no matter whether there's a ring transition. Jan