From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Jan Beulich" Subject: [PATCH] increase default console ring allocation size and reduce default verbosity Date: Tue, 16 Mar 2010 16:27:09 +0000 Message-ID: <4B9FBF6D0200007800035389@vpn.id2.novell.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="=__Part406A994D.0__=" Return-path: List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: xen-devel@lists.xensource.com List-Id: xen-devel@lists.xenproject.org This is a MIME message. If you are reading this text, you may want to consider changing to a mail reader or gateway that understands how to properly handle MIME multipart messages. --=__Part406A994D.0__= Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Content-Disposition: inline In order to have better chance that relevant messages fit into the ring buffer, allocate a dynamic (larger) one in more cases, and make the default allocation size depend on both the number of CPUs and the log level. Also free the static buffer if a dynamic one was obtained. In order for "xm dmesg" to retrieve larger buffers, eliminate pyxc_readconsolering()'s 32k limitation resulting from the use of a statically allocated buffer. Finally, suppress on x86 most per-CPU boot time messages (by default, most of them can be re-enabled with a new command line option "cpuinfo", some others are now only printed more than once when there are inconsistencies between CPUs). This reduces both boot time (namely when a graphical console is in use) and pressure on the console ring and serial transmit buffers. Signed-off-by: Jan Beulich --- 2010-03-02.orig/tools/python/xen/lowlevel/xc/xc.c 2010-03-16 = 16:18:34.000000000 +0100 +++ 2010-03-02/tools/python/xen/lowlevel/xc/xc.c 2010-03-16 = 16:29:22.000000000 +0100 @@ -1062,14 +1062,16 @@ static PyObject *pyxc_readconsolering(Xc PyObject *kwds) { unsigned int clear =3D 0, index =3D 0, incremental =3D 0; - char _str[32768], *str =3D _str; - unsigned int count =3D 32768; + unsigned int count =3D 16384 + 1, size =3D count; + char *str =3D malloc(size), *ptr; + PyObject *obj; int ret; =20 static char *kwd_list[] =3D { "clear", "index", "incremental", NULL = }; =20 if ( !PyArg_ParseTupleAndKeywords(args, kwds, "|iii", kwd_list, - &clear, &index, &incremental) ) + &clear, &index, &incremental) || + !str ) return NULL; =20 ret =3D xc_readconsolering(self->xc_handle, &str, &count, clear, @@ -1077,7 +1079,30 @@ static PyObject *pyxc_readconsolering(Xc if ( ret < 0 ) return pyxc_error_to_exception(); =20 - return PyString_FromStringAndSize(str, count); + while ( !incremental && count =3D=3D size ) + { + size +=3D count - 1; + if ( size < count ) + break; + + ptr =3D realloc(str, size); + if ( !ptr ) + break; + + str =3D ptr + count; + count =3D size - count; + ret =3D xc_readconsolering(self->xc_handle, &str, &count, clear, + 1, &index); + if ( ret < 0 ) + break; + + count +=3D str - ptr; + str =3D ptr; + } + + obj =3D PyString_FromStringAndSize(str, count); + free(str); + return obj; } =20 =20 --- 2010-03-02.orig/xen/arch/ia64/xen/xen.lds.S 2009-07-13 13:05:40.0000000= 00 +0200 +++ 2010-03-02/xen/arch/ia64/xen/xen.lds.S 2010-03-16 16:43:48.0000000= 00 +0100 @@ -223,7 +223,12 @@ SECTIONS .sbss : AT(ADDR(.sbss) - LOAD_OFFSET) { *(.sbss) *(.scommon) } .bss : AT(ADDR(.bss) - LOAD_OFFSET) - { *(.bss) *(COMMON) } + { + . =3D ALIGN(PAGE_SIZE); + *(.bss.page_aligned) + *(.bss) + *(COMMON) + } =20 _end =3D .; =20 --- 2010-03-02.orig/xen/arch/x86/cpu/amd.c 2010-03-16 16:18:34.0000000= 00 +0100 +++ 2010-03-02/xen/arch/x86/cpu/amd.c 2010-03-16 10:54:10.000000000 = +0100 @@ -493,8 +493,9 @@ static void __devinit init_amd(struct cp } cpu_core_id[cpu] =3D phys_proc_id[cpu] & ((1<>=3D bits; - printk(KERN_INFO "CPU %d(%d) -> Core %d\n", - cpu, c->x86_max_cores, cpu_core_id[cpu]); + if (opt_cpu_info) + printk("CPU %d(%d) -> Core %d\n", + cpu, c->x86_max_cores, cpu_core_id[cpu]); } #endif =20 --- 2010-03-02.orig/xen/arch/x86/cpu/common.c 2010-03-16 16:18:34.0000000= 00 +0100 +++ 2010-03-02/xen/arch/x86/cpu/common.c 2010-03-16 10:53:55.0000000= 00 +0100 @@ -59,6 +59,9 @@ static struct cpu_dev * this_cpu =3D &defa =20 integer_param("cachesize", cachesize_override); =20 +int __cpuinitdata opt_cpu_info; +boolean_param("cpuinfo", opt_cpu_info); + int __cpuinit get_model_name(struct cpuinfo_x86 *c) { unsigned int *v; @@ -97,8 +100,10 @@ void __cpuinit display_cacheinfo(struct=20 =20 if (n >=3D 0x80000005) { cpuid(0x80000005, &dummy, &dummy, &ecx, &edx); - printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D = cache %dK (%d bytes/line)\n", - edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); + if (opt_cpu_info) + printk("CPU: L1 I cache %dK (%d bytes/line)," + " D cache %dK (%d bytes/line)\n", + edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); c->x86_cache_size=3D(ecx>>24)+(edx>>24);=09 } =20 @@ -121,8 +126,9 @@ void __cpuinit display_cacheinfo(struct=20 =20 c->x86_cache_size =3D l2size; =20 - printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", - l2size, ecx & 0xFF); + if (opt_cpu_info) + printk("CPU: L2 Cache: %dK (%d bytes/line)\n", + l2size, ecx & 0xFF); } =20 /* Naming convention should be: [()] */ @@ -495,8 +501,9 @@ void __cpuinit detect_ht(struct cpuinfo_ index_msb =3D get_count_order(c->x86_num_siblings); phys_proc_id[cpu] =3D phys_pkg_id((ebx >> 24) & 0xFF, = index_msb); =20 - printk(KERN_INFO "CPU: Physical Processor ID: %d\n", - phys_proc_id[cpu]); + if (opt_cpu_info) + printk("CPU: Physical Processor ID: %d\n", + phys_proc_id[cpu]); =20 c->x86_num_siblings =3D c->x86_num_siblings / c->x86_max_co= res; =20 @@ -507,16 +514,22 @@ void __cpuinit detect_ht(struct cpuinfo_ cpu_core_id[cpu] =3D phys_pkg_id((ebx >> 24) & 0xFF, = index_msb) & ((1 << core_bits) - 1); =20 - if (c->x86_max_cores > 1) - printk(KERN_INFO "CPU: Processor Core ID: %d\n", + if (opt_cpu_info && c->x86_max_cores > 1) + printk("CPU: Processor Core ID: %d\n", cpu_core_id[cpu]); } } #endif =20 -void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) +void __cpuinit print_cpu_info(unsigned int cpu) { - char *vendor =3D NULL; + const struct cpuinfo_x86 *c =3D cpu_data + cpu; + const char *vendor =3D NULL; + + if (!opt_cpu_info) + return; + + printk("CPU%u: ", cpu); =20 if (c->x86_vendor < X86_VENDOR_NUM) vendor =3D this_cpu->c_vendor; @@ -578,7 +591,8 @@ void __cpuinit cpu_init(void) printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); for (;;) local_irq_enable(); } - printk(KERN_INFO "Initializing CPU#%d\n", cpu); + if (opt_cpu_info) + printk("Initializing CPU#%d\n", cpu); =20 if (cpu_has_pat) wrmsrl(MSR_IA32_CR_PAT, host_pat); --- 2010-03-02.orig/xen/arch/x86/cpu/intel_cacheinfo.c 2010-03-16 = 16:18:34.000000000 +0100 +++ 2010-03-02/xen/arch/x86/cpu/intel_cacheinfo.c 2010-03-16 = 10:54:50.000000000 +0100 @@ -415,21 +415,23 @@ unsigned int __cpuinit init_intel_cachei l3 =3D new_l3; } =20 - if (trace) - printk (KERN_INFO "CPU: Trace cache: %dK uops", trace); - else if ( l1i ) - printk (KERN_INFO "CPU: L1 I cache: %dK", l1i); - - if (l1d) - printk(", L1 D cache: %dK\n", l1d); - else - printk("\n"); + if (opt_cpu_info) { + if (trace) + printk("CPU: Trace cache: %dK uops", trace); + else if ( l1i ) + printk("CPU: L1 I cache: %dK", l1i); + + if (l1d) + printk(", L1 D cache: %dK\n", l1d); + else + printk("\n"); =20 - if (l2) - printk(KERN_INFO "CPU: L2 cache: %dK\n", l2); + if (l2) + printk("CPU: L2 cache: %dK\n", l2); =20 - if (l3) - printk(KERN_INFO "CPU: L3 cache: %dK\n", l3); + if (l3) + printk("CPU: L3 cache: %dK\n", l3); + } =20 c->x86_cache_size =3D l3 ? l3 : (l2 ? l2 : (l1i+l1d)); =20 --- 2010-03-02.orig/xen/arch/x86/cpu/mcheck/amd_f10.c 2010-03-16 = 16:18:34.000000000 +0100 +++ 2010-03-02/xen/arch/x86/cpu/mcheck/amd_f10.c 2010-03-16 = 09:59:18.000000000 +0100 @@ -83,15 +83,12 @@ amd_f10_handler(struct mc_info *mi, uint } =20 /* AMD Family10 machine check */ -int amd_f10_mcheck_init(struct cpuinfo_x86 *c)=20 +enum mcheck_type amd_f10_mcheck_init(struct cpuinfo_x86 *c) {=20 - if (!amd_k8_mcheck_init(c)) - return 0; + if (amd_k8_mcheck_init(c) =3D=3D mcheck_none) + return mcheck_none; =20 x86_mce_callback_register(amd_f10_handler); =20 - printk("CPU%i: AMD Family%xh machine check reporting enabled\n", - smp_processor_id(), c->x86); - - return 1; + return mcheck_amd_famXX; } --- 2010-03-02.orig/xen/arch/x86/cpu/mcheck/amd_k8.c 2010-03-16 = 16:18:34.000000000 +0100 +++ 2010-03-02/xen/arch/x86/cpu/mcheck/amd_k8.c 2010-03-16 09:28:25.0000000= 00 +0100 @@ -76,14 +76,14 @@ static void k8_machine_check(struct cpu_ } =20 /* AMD K8 machine check */ -int amd_k8_mcheck_init(struct cpuinfo_x86 *c) +enum mcheck_type amd_k8_mcheck_init(struct cpuinfo_x86 *c) { uint32_t i; enum mcequirk_amd_flags quirkflag; =20 /* Check for PPro style MCA; our caller has confirmed MCE support. = */ if (!cpu_has(c, X86_FEATURE_MCA)) - return 0; + return mcheck_none; =20 quirkflag =3D mcequirk_lookup_amd_quirkdata(c); =20 @@ -102,9 +102,6 @@ int amd_k8_mcheck_init(struct cpuinfo_x8 } =20 set_in_cr4(X86_CR4_MCE); - if (c->x86 < 0x10 || c->x86 > 0x11) - printk("CPU%i: AMD K8 machine check reporting enabled\n", - smp_processor_id()); =20 - return 1; + return mcheck_amd_k8; } --- 2010-03-02.orig/xen/arch/x86/cpu/mcheck/k7.c 2010-03-16 = 16:18:34.000000000 +0100 +++ 2010-03-02/xen/arch/x86/cpu/mcheck/k7.c 2010-03-16 09:28:04.0000000= 00 +0100 @@ -68,14 +68,14 @@ static fastcall void k7_machine_check(st =20 =20 /* AMD K7 machine check */ -int amd_k7_mcheck_init(struct cpuinfo_x86 *c) +enum mcheck_type amd_k7_mcheck_init(struct cpuinfo_x86 *c) { u32 l, h; int i; =20 /* Check for PPro style MCA; our caller has confirmed MCE support. = */ if (!cpu_has(c, X86_FEATURE_MCA)) - return 0; + return mcheck_none; =20 x86_mce_vector_register(k7_machine_check); =20 @@ -93,8 +93,6 @@ int amd_k7_mcheck_init(struct cpuinfo_x8 } =20 set_in_cr4 (X86_CR4_MCE); - printk (KERN_INFO "CPU%d: AMD K7 machine check reporting enabled.\n= ", - smp_processor_id()); =20 - return 1; + return mcheck_amd_k7; } --- 2010-03-02.orig/xen/arch/x86/cpu/mcheck/mce.c 2010-03-16 = 16:18:34.000000000 +0100 +++ 2010-03-02/xen/arch/x86/cpu/mcheck/mce.c 2010-03-16 09:59:41.0000000= 00 +0100 @@ -562,9 +562,9 @@ void mcheck_mca_clearbanks(cpu_banks_t b } } =20 -static int amd_mcheck_init(struct cpuinfo_x86 *ci) +static enum mcheck_type amd_mcheck_init(struct cpuinfo_x86 *ci) { - int rc =3D 0; + enum mcheck_type rc =3D mcheck_none; =20 switch (ci->x86) { case 6: @@ -628,7 +628,9 @@ int mce_firstbank(struct cpuinfo_x86 *c) /* This has to be run for each processor */ void mcheck_init(struct cpuinfo_x86 *c) { - int inited =3D 0, i, broadcast; + int i, broadcast; + enum mcheck_type inited =3D mcheck_none; + static enum mcheck_type g_type =3D mcheck_unset; static int broadcast_check; =20 if (mce_disabled =3D=3D 1) { @@ -694,9 +696,37 @@ void mcheck_init(struct cpuinfo_x86 *c) if (g_mcg_cap & MCG_CTL_P) rdmsrl(MSR_IA32_MCG_CTL, h_mcg_ctl); set_poll_bankmask(c); - if (!inited) - printk(XENLOG_INFO "CPU%i: No machine check initialization\= n", - smp_processor_id()); + + if (inited !=3D g_type) { + char prefix[20]; + static const char *const type_str[] =3D { + [mcheck_amd_famXX] =3D "AMD", + [mcheck_amd_k7] =3D "AMD K7", + [mcheck_amd_k8] =3D "AMD K8", + [mcheck_intel] =3D "Intel" + }; + + snprintf(prefix, ARRAY_SIZE(prefix), + g_type !=3D mcheck_unset ? XENLOG_WARNING "CPU%i: = " + : XENLOG_INFO, + smp_processor_id()); + BUG_ON(inited >=3D ARRAY_SIZE(type_str)); + switch (inited) { + default: + printk("%s%s machine check reporting enabled\n", + prefix, type_str[inited]); + break; + case mcheck_amd_famXX: + printk("%s%s Fam%xh machine check reporting = enabled\n", + prefix, type_str[inited], c->x86); + break; + case mcheck_none: + printk("%sNo machine check initialization\n", = prefix); + break; + } + + g_type =3D inited; + } } =20 u64 mce_cap_init(void) --- 2010-03-02.orig/xen/arch/x86/cpu/mcheck/mce.h 2010-03-16 = 16:18:34.000000000 +0100 +++ 2010-03-02/xen/arch/x86/cpu/mcheck/mce.h 2010-03-16 09:25:22.0000000= 00 +0100 @@ -28,13 +28,21 @@ extern int mce_verbosity; printk(s, ##a); \ } while (0) =20 +enum mcheck_type { + mcheck_unset =3D -1, + mcheck_none, + mcheck_amd_famXX, + mcheck_amd_k7, + mcheck_amd_k8, + mcheck_intel +}; =20 /* Init functions */ -int amd_k7_mcheck_init(struct cpuinfo_x86 *c); -int amd_k8_mcheck_init(struct cpuinfo_x86 *c); -int amd_f10_mcheck_init(struct cpuinfo_x86 *c); +enum mcheck_type amd_k7_mcheck_init(struct cpuinfo_x86 *c); +enum mcheck_type amd_k8_mcheck_init(struct cpuinfo_x86 *c); +enum mcheck_type amd_f10_mcheck_init(struct cpuinfo_x86 *c); =20 -int intel_mcheck_init(struct cpuinfo_x86 *c); +enum mcheck_type intel_mcheck_init(struct cpuinfo_x86 *c); =20 void intel_mcheck_timer(struct cpuinfo_x86 *c); void mce_intel_feature_init(struct cpuinfo_x86 *c); --- 2010-03-02.orig/xen/arch/x86/cpu/mcheck/mce_intel.c 2010-03-16 = 16:18:34.000000000 +0100 +++ 2010-03-02/xen/arch/x86/cpu/mcheck/mce_intel.c 2010-03-16 = 17:11:44.000000000 +0100 @@ -141,8 +141,9 @@ static void intel_init_thermal(struct cp =20 l =3D apic_read (APIC_LVTTHMR); apic_write_around (APIC_LVTTHMR, l & ~APIC_LVT_MASKED); - printk (KERN_INFO "CPU%d: Thermal monitoring enabled (%s)\n",=20 - cpu, tm2 ? "TM2" : "TM1"); + if (opt_cpu_info) + printk(KERN_INFO "CPU%u: Thermal monitoring enabled (%s)\n", + cpu, tm2 ? "TM2" : "TM1"); return; } #endif /* CONFIG_X86_MCE_THERMAL */ @@ -946,7 +947,8 @@ static void intel_init_cmci(struct cpuin int cpu =3D smp_processor_id(); =20 if (!mce_available(c) || !cmci_support) { - mce_printk(MCE_QUIET, "CMCI: CPU%d has no CMCI support\n", cpu); + if (opt_cpu_info) + mce_printk(MCE_QUIET, "CMCI: CPU%d has no CMCI support\n", = cpu); return; } =20 @@ -1068,11 +1070,9 @@ static void mce_init(void) } =20 /* p4/p6 family have similar MCA initialization process */ -int intel_mcheck_init(struct cpuinfo_x86 *c) +enum mcheck_type intel_mcheck_init(struct cpuinfo_x86 *c) { _mce_cap_init(c); - mce_printk(MCE_QUIET, "Intel machine check reporting enabled on = CPU#%d.\n", - smp_processor_id()); =20 /* machine check is available */ x86_mce_vector_register(intel_machine_check); @@ -1085,7 +1085,7 @@ int intel_mcheck_init(struct cpuinfo_x86 mce_set_owner(); =20 open_softirq(MACHINE_CHECK_SOFTIRQ, mce_softirq); - return 1; + return mcheck_intel; } =20 int intel_mce_wrmsr(uint32_t msr, uint64_t val) --- 2010-03-02.orig/xen/arch/x86/hvm/asid.c 2010-03-16 16:18:34.0000000= 00 +0100 +++ 2010-03-02/xen/arch/x86/hvm/asid.c 2010-03-15 17:41:13.000000000 = +0100 @@ -59,6 +59,7 @@ static DEFINE_PER_CPU(struct hvm_asid_da =20 void hvm_asid_init(int nasids) { + static s8 g_disabled =3D -1; struct hvm_asid_data *data =3D &this_cpu(hvm_asid_data); =20 /* @@ -72,8 +73,12 @@ void hvm_asid_init(int nasids) data->max_asid =3D nasids - 1; data->disabled =3D (nasids <=3D 1); =20 - printk("HVM: ASIDs %s \n", - (data->disabled ? "disabled." : "enabled.")); + if ( g_disabled !=3D data->disabled ) + { + printk("HVM: ASIDs %sabled.\n", data->disabled ? "dis" : "en"); + if ( g_disabled < 0 ) + g_disabled =3D data->disabled; + } =20 /* Zero indicates 'invalid generation', so we start the count at one. = */ data->core_asid_generation =3D 1; --- 2010-03-02.orig/xen/arch/x86/setup.c 2010-03-16 16:18:34.0000000= 00 +0100 +++ 2010-03-02/xen/arch/x86/setup.c 2010-03-16 10:55:07.000000000 = +0100 @@ -269,8 +269,8 @@ void __devinit srat_detect_node(int cpu) node =3D 0; numa_set_node(cpu, node); =20 - if ( acpi_numa > 0 ) - printk(KERN_INFO "CPU %d APIC %d -> Node %d\n", cpu, apicid, = node); + if ( opt_cpu_info && acpi_numa > 0 ) + printk("CPU %d APIC %d -> Node %d\n", cpu, apicid, node); } =20 /* --- 2010-03-02.orig/xen/arch/x86/smpboot.c 2010-03-16 16:18:34.0000000= 00 +0100 +++ 2010-03-02/xen/arch/x86/smpboot.c 2010-03-16 09:16:52.000000000 = +0100 @@ -877,7 +877,9 @@ static int __devinit do_boot_cpu(int api start_eip =3D setup_trampoline(); =20 /* So we see what's up */ - printk("Booting processor %d/%d eip %lx\n", cpu, apicid, start_eip)= ; + if (opt_cpu_info) + printk("Booting processor %d/%d eip %lx\n", + cpu, apicid, start_eip); =20 stack_start.esp =3D prepare_idle_stack(cpu); =20 @@ -960,8 +962,7 @@ static int __devinit do_boot_cpu(int api if (cpu_isset(cpu, cpu_callin_map)) { /* number CPUs logically, starting from 1 (BSP is = 0) */ Dprintk("OK.\n"); - printk("CPU%d: ", cpu); - print_cpu_info(&cpu_data[cpu]); + print_cpu_info(cpu); Dprintk("CPU has booted.\n"); } else { boot_error =3D 1; @@ -1062,8 +1063,7 @@ static void __init smp_boot_cpus(unsigne * Setup boot CPU information */ smp_store_cpu_info(0); /* Final full version of the data */ - printk("CPU%d: ", 0); - print_cpu_info(&cpu_data[0]); + print_cpu_info(0); =20 boot_cpu_physical_apicid =3D get_apic_id(); x86_cpu_to_apicid[0] =3D boot_cpu_physical_apicid; --- 2010-03-02.orig/xen/drivers/char/console.c 2010-03-16 16:18:39.0000000= 00 +0100 +++ 2010-03-02/xen/drivers/char/console.c 2010-03-16 16:41:10.0000000= 00 +0100 @@ -65,7 +65,12 @@ size_param("conring_size", opt_conring_s =20 #define _CONRING_SIZE 16384 #define CONRING_IDX_MASK(i) ((i)&(conring_size-1)) -static char _conring[_CONRING_SIZE], *__read_mostly conring =3D _conring; +static char +#if _CONRING_SIZE >=3D PAGE_SIZE + __attribute__((__section__(".bss.page_aligned"), __aligned__(PAGE_SIZE= ))) +#endif + _conring[_CONRING_SIZE]; +static char *__read_mostly conring =3D _conring; static uint32_t __read_mostly conring_size =3D _CONRING_SIZE; static uint32_t conringc, conringp; =20 @@ -595,6 +600,8 @@ void __init console_init_postirq(void) =20 serial_init_postirq(); =20 + if ( !opt_conring_size ) + opt_conring_size =3D num_present_cpus() << (9 + xenlog_lower_thres= h); /* Round size down to a power of two. */ while ( opt_conring_size & (opt_conring_size - 1) ) opt_conring_size &=3D opt_conring_size - 1; @@ -618,6 +625,8 @@ void __init console_init_postirq(void) spin_unlock_irq(&console_lock); =20 printk("Allocated console ring of %u KiB.\n", opt_conring_size >> = 10); + + init_xenheap_pages(__pa(_conring), __pa(_conring + _CONRING_SIZE)); } =20 void __init console_endboot(void) --- 2010-03-02.orig/xen/include/asm-x86/processor.h 2010-03-16 = 16:18:34.000000000 +0100 +++ 2010-03-02/xen/include/asm-x86/processor.h 2010-03-15 17:55:08.0000000= 00 +0100 @@ -194,10 +194,11 @@ extern struct cpuinfo_x86 cpu_data[]; extern u64 host_pat; extern int phys_proc_id[NR_CPUS]; extern int cpu_core_id[NR_CPUS]; +extern int opt_cpu_info; =20 extern void identify_cpu(struct cpuinfo_x86 *); extern void setup_clear_cpu_cap(unsigned int); -extern void print_cpu_info(struct cpuinfo_x86 *); +extern void print_cpu_info(unsigned int cpu); extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c); extern void dodgy_tsc(void); =20 --=__Part406A994D.0__= Content-Type: text/plain; name="default-buffer-sizes.patch" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="default-buffer-sizes.patch" In order to have better chance that relevant messages fit into the=0Aring = buffer, allocate a dynamic (larger) one in more cases, and make=0Athe = default allocation size depend on both the number of CPUs and the=0Alog = level. Also free the static buffer if a dynamic one was obtained.=0A=0AIn = order for "xm dmesg" to retrieve larger buffers, eliminate=0Apyxc_readconso= lering()'s 32k limitation resulting from the use of a=0Astatically = allocated buffer.=0A=0AFinally, suppress on x86 most per-CPU boot time = messages (by default,=0Amost of them can be re-enabled with a new command = line option=0A"cpuinfo", some others are now only printed more than once = when there=0Aare inconsistencies between CPUs). This reduces both boot = time (namely=0Awhen a graphical console is in use) and pressure on the = console ring=0Aand serial transmit buffers.=0A=0ASigned-off-by: Jan = Beulich =0A=0A--- 2010-03-02.orig/tools/python/xen/low= level/xc/xc.c 2010-03-16 16:18:34.000000000 +0100=0A+++ 2010-03-02/tools/= python/xen/lowlevel/xc/xc.c 2010-03-16 16:29:22.000000000 +0100=0A@@ = -1062,14 +1062,16 @@ static PyObject *pyxc_readconsolering(Xc=0A = PyObject *kwds)=0A {=0A unsigned int clear = =3D 0, index =3D 0, incremental =3D 0;=0A- char _str[32768], = *str =3D _str;=0A- unsigned int count =3D 32768;=0A+ unsigned int = count =3D 16384 + 1, size =3D count;=0A+ char *str =3D malloc(siz= e), *ptr;=0A+ PyObject *obj;=0A int ret;=0A =0A = static char *kwd_list[] =3D { "clear", "index", "incremental", NULL };=0A = =0A if ( !PyArg_ParseTupleAndKeywords(args, kwds, "|iii", kwd_list,=0A-= &clear, &index, &incremental) )=0A+ = &clear, &index, &incremental) ||=0A+ = !str )=0A return NULL;=0A =0A ret =3D xc_readconsolering(= self->xc_handle, &str, &count, clear,=0A@@ -1077,7 +1079,30 @@ static = PyObject *pyxc_readconsolering(Xc=0A if ( ret < 0 )=0A return = pyxc_error_to_exception();=0A =0A- return PyString_FromStringAndSize(str= , count);=0A+ while ( !incremental && count =3D=3D size )=0A+ {=0A+ = size +=3D count - 1;=0A+ if ( size < count )=0A+ = break;=0A+=0A+ ptr =3D realloc(str, size);=0A+ if ( !ptr = )=0A+ break;=0A+=0A+ str =3D ptr + count;=0A+ = count =3D size - count;=0A+ ret =3D xc_readconsolering(self->xc_hand= le, &str, &count, clear,=0A+ 1, &index);=0A= + if ( ret < 0 )=0A+ break;=0A+=0A+ count +=3D = str - ptr;=0A+ str =3D ptr;=0A+ }=0A+=0A+ obj =3D PyString_Fro= mStringAndSize(str, count);=0A+ free(str);=0A+ return obj;=0A }=0A = =0A =0A--- 2010-03-02.orig/xen/arch/ia64/xen/xen.lds.S 2009-07-13 = 13:05:40.000000000 +0200=0A+++ 2010-03-02/xen/arch/ia64/xen/xen.lds.S = 2010-03-16 16:43:48.000000000 +0100=0A@@ -223,7 +223,12 @@ SECTIONS=0A = .sbss : AT(ADDR(.sbss) - LOAD_OFFSET)=0A { *(.sbss) *(.scommon) = }=0A .bss : AT(ADDR(.bss) - LOAD_OFFSET)=0A- { *(.bss) *(COMMON) }=0A+ = {=0A+ . =3D ALIGN(PAGE_SIZE);=0A+ *(.bss.page_aligned= )=0A+ *(.bss)=0A+ *(COMMON)=0A+ }=0A =0A _end = =3D .;=0A =0A--- 2010-03-02.orig/xen/arch/x86/cpu/amd.c 2010-03-16 = 16:18:34.000000000 +0100=0A+++ 2010-03-02/xen/arch/x86/cpu/amd.c = 2010-03-16 10:54:10.000000000 +0100=0A@@ -493,8 +493,9 @@ static void = __devinit init_amd(struct cp=0A }=0A cpu_core_id= [cpu] =3D phys_proc_id[cpu] & ((1<>=3D bits;=0A- printk(KERN_INFO "CPU %d(%d) -> Core = %d\n",=0A- cpu, c->x86_max_cores, cpu_core_id[cpu]);=0A= + if (opt_cpu_info)=0A+ printk("CPU %d(%d) = -> Core %d\n",=0A+ cpu, c->x86_max_cores, = cpu_core_id[cpu]);=0A }=0A #endif=0A =0A--- 2010-03-02.orig/xen/arch/x86/= cpu/common.c 2010-03-16 16:18:34.000000000 +0100=0A+++ 2010-03-02/xen/ar= ch/x86/cpu/common.c 2010-03-16 10:53:55.000000000 +0100=0A@@ -59,6 = +59,9 @@ static struct cpu_dev * this_cpu =3D &defa=0A =0A integer_param("c= achesize", cachesize_override);=0A =0A+int __cpuinitdata opt_cpu_info;=0A+b= oolean_param("cpuinfo", opt_cpu_info);=0A+=0A int __cpuinit get_model_name(= struct cpuinfo_x86 *c)=0A {=0A unsigned int *v;=0A@@ -97,8 +100,10 @@ = void __cpuinit display_cacheinfo(struct =0A =0A if (n >=3D = 0x80000005) {=0A cpuid(0x80000005, &dummy, &dummy, &ecx, = &edx);=0A- printk(KERN_INFO "CPU: L1 I Cache: %dK (%d = bytes/line), D cache %dK (%d bytes/line)\n",=0A- = edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);=0A+ if (opt_cpu_info)= =0A+ printk("CPU: L1 I cache %dK (%d bytes/line),"=0A+ = " D cache %dK (%d bytes/line)\n",=0A+ = edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);=0A = c->x86_cache_size=3D(ecx>>24)+(edx>>24); =0A }=0A =0A@@ -121,8 = +126,9 @@ void __cpuinit display_cacheinfo(struct =0A =0A c->x86_cach= e_size =3D l2size;=0A =0A- printk(KERN_INFO "CPU: L2 Cache: %dK (%d = bytes/line)\n",=0A- l2size, ecx & 0xFF);=0A+ if (opt_cpu_info)= =0A+ printk("CPU: L2 Cache: %dK (%d bytes/line)\n",=0A+ = l2size, ecx & 0xFF);=0A }=0A =0A /* Naming convention should be: = [()] */=0A@@ -495,8 +501,9 @@ void __cpuinit detect_ht(str= uct cpuinfo_=0A index_msb =3D get_count_order(c->x86_num_si= blings);=0A phys_proc_id[cpu] =3D phys_pkg_id((ebx >> 24) & = 0xFF, index_msb);=0A =0A- printk(KERN_INFO "CPU: Physical = Processor ID: %d\n",=0A- phys_proc_id[cpu]);=0A+ = if (opt_cpu_info)=0A+ printk("CPU: Physical Processor = ID: %d\n",=0A+ phys_proc_id[cpu]);=0A =0A = c->x86_num_siblings =3D c->x86_num_siblings / c->x86_max_cores;=0A =0A@@ = -507,16 +514,22 @@ void __cpuinit detect_ht(struct cpuinfo_=0A = cpu_core_id[cpu] =3D phys_pkg_id((ebx >> 24) & 0xFF, index_msb) &=0A = ((1 << core_bits) - 1);=0A =0A- if = (c->x86_max_cores > 1)=0A- printk(KERN_INFO "CPU: = Processor Core ID: %d\n",=0A+ if (opt_cpu_info && c->x86_max_core= s > 1)=0A+ printk("CPU: Processor Core ID: %d\n",=0A = cpu_core_id[cpu]);=0A }=0A }=0A #endif=0A = =0A-void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)=0A+void __cpuinit = print_cpu_info(unsigned int cpu)=0A {=0A- char *vendor =3D NULL;=0A+ = const struct cpuinfo_x86 *c =3D cpu_data + cpu;=0A+ const char *vendor = =3D NULL;=0A+=0A+ if (!opt_cpu_info)=0A+ return;=0A+=0A+ = printk("CPU%u: ", cpu);=0A =0A if (c->x86_vendor < X86_VENDOR_NUM)=0A = vendor =3D this_cpu->c_vendor;=0A@@ -578,7 +591,8 @@ void __cpuinit = cpu_init(void)=0A printk(KERN_WARNING "CPU#%d already = initialized!\n", cpu);=0A for (;;) local_irq_enable();=0A = }=0A- printk(KERN_INFO "Initializing CPU#%d\n", cpu);=0A+ if = (opt_cpu_info)=0A+ printk("Initializing CPU#%d\n", cpu);=0A = =0A if (cpu_has_pat)=0A wrmsrl(MSR_IA32_CR_PAT, host_pat);= =0A--- 2010-03-02.orig/xen/arch/x86/cpu/intel_cacheinfo.c 2010-03-16 = 16:18:34.000000000 +0100=0A+++ 2010-03-02/xen/arch/x86/cpu/intel_cacheinfo.= c 2010-03-16 10:54:50.000000000 +0100=0A@@ -415,21 +415,23 @@ = unsigned int __cpuinit init_intel_cachei=0A l3 =3D new_l3;=0A = }=0A =0A- if (trace)=0A- printk (KERN_INFO "CPU: Trace = cache: %dK uops", trace);=0A- else if ( l1i )=0A- printk = (KERN_INFO "CPU: L1 I cache: %dK", l1i);=0A-=0A- if (l1d)=0A- = printk(", L1 D cache: %dK\n", l1d);=0A- else=0A- printk("\n"= );=0A+ if (opt_cpu_info) {=0A+ if (trace)=0A+ = printk("CPU: Trace cache: %dK uops", trace);=0A+ else if ( = l1i )=0A+ printk("CPU: L1 I cache: %dK", l1i);=0A+=0A= + if (l1d)=0A+ printk(", L1 D cache: = %dK\n", l1d);=0A+ else=0A+ printk("\n"= );=0A =0A- if (l2)=0A- printk(KERN_INFO "CPU: L2 cache: = %dK\n", l2);=0A+ if (l2)=0A+ printk("CPU= : L2 cache: %dK\n", l2);=0A =0A- if (l3)=0A- printk(KERN= _INFO "CPU: L3 cache: %dK\n", l3);=0A+ if (l3)=0A+ = printk("CPU: L3 cache: %dK\n", l3);=0A+ }=0A =0A c->x86_cache_size = =3D l3 ? l3 : (l2 ? l2 : (l1i+l1d));=0A =0A--- 2010-03-02.orig/xen/arch/x86= /cpu/mcheck/amd_f10.c 2010-03-16 16:18:34.000000000 +0100=0A+++ = 2010-03-02/xen/arch/x86/cpu/mcheck/amd_f10.c 2010-03-16 09:59:18.0000000= 00 +0100=0A@@ -83,15 +83,12 @@ amd_f10_handler(struct mc_info *mi, uint=0A = }=0A =0A /* AMD Family10 machine check */=0A-int amd_f10_mcheck_init(struct= cpuinfo_x86 *c) =0A+enum mcheck_type amd_f10_mcheck_init(struct cpuinfo_x8= 6 *c)=0A { =0A- if (!amd_k8_mcheck_init(c))=0A- return 0;=0A+ if = (amd_k8_mcheck_init(c) =3D=3D mcheck_none)=0A+ return mcheck_none;= =0A =0A x86_mce_callback_register(amd_f10_handler);=0A =0A- = printk("CPU%i: AMD Family%xh machine check reporting enabled\n",=0A- = smp_processor_id(), c->x86);=0A-=0A- return 1;=0A+ return = mcheck_amd_famXX;=0A }=0A--- 2010-03-02.orig/xen/arch/x86/cpu/mcheck/amd_k8= .c 2010-03-16 16:18:34.000000000 +0100=0A+++ 2010-03-02/xen/arch/x86/c= pu/mcheck/amd_k8.c 2010-03-16 09:28:25.000000000 +0100=0A@@ -76,14 = +76,14 @@ static void k8_machine_check(struct cpu_=0A }=0A =0A /* AMD K8 = machine check */=0A-int amd_k8_mcheck_init(struct cpuinfo_x86 *c)=0A+enum = mcheck_type amd_k8_mcheck_init(struct cpuinfo_x86 *c)=0A {=0A uint32_t = i;=0A enum mcequirk_amd_flags quirkflag;=0A =0A /* Check for PPro = style MCA; our caller has confirmed MCE support. */=0A if (!cpu_has(c, = X86_FEATURE_MCA))=0A- return 0;=0A+ return mcheck_none;= =0A =0A quirkflag =3D mcequirk_lookup_amd_quirkdata(c);=0A =0A@@ = -102,9 +102,6 @@ int amd_k8_mcheck_init(struct cpuinfo_x8=0A }=0A =0A = set_in_cr4(X86_CR4_MCE);=0A- if (c->x86 < 0x10 || c->x86 > 0x11)=0A- = printk("CPU%i: AMD K8 machine check reporting enabled\n",=0A- = smp_processor_id());=0A =0A- return 1;=0A+ return mcheck_amd_k= 8;=0A }=0A--- 2010-03-02.orig/xen/arch/x86/cpu/mcheck/k7.c 2010-03-16 = 16:18:34.000000000 +0100=0A+++ 2010-03-02/xen/arch/x86/cpu/mcheck/k7.c = 2010-03-16 09:28:04.000000000 +0100=0A@@ -68,14 +68,14 @@ static fastcall = void k7_machine_check(st=0A =0A =0A /* AMD K7 machine check */=0A-int = amd_k7_mcheck_init(struct cpuinfo_x86 *c)=0A+enum mcheck_type amd_k7_mcheck= _init(struct cpuinfo_x86 *c)=0A {=0A u32 l, h;=0A int i;=0A =0A /* = Check for PPro style MCA; our caller has confirmed MCE support. */=0A if = (!cpu_has(c, X86_FEATURE_MCA))=0A- return 0;=0A+ = return mcheck_none;=0A =0A x86_mce_vector_register(k7_machine_check);= =0A =0A@@ -93,8 +93,6 @@ int amd_k7_mcheck_init(struct cpuinfo_x8=0A = }=0A =0A set_in_cr4 (X86_CR4_MCE);=0A- printk (KERN_INFO "CPU%d: = AMD K7 machine check reporting enabled.\n",=0A- smp_processor_id())= ;=0A =0A- return 1;=0A+ return mcheck_amd_k7;=0A }=0A--- 2010-03-02= .orig/xen/arch/x86/cpu/mcheck/mce.c 2010-03-16 16:18:34.000000000 = +0100=0A+++ 2010-03-02/xen/arch/x86/cpu/mcheck/mce.c 2010-03-16 = 09:59:41.000000000 +0100=0A@@ -562,9 +562,9 @@ void mcheck_mca_clearbanks(c= pu_banks_t b=0A }=0A }=0A =0A-static int amd_mcheck_init(struct = cpuinfo_x86 *ci)=0A+static enum mcheck_type amd_mcheck_init(struct = cpuinfo_x86 *ci)=0A {=0A- int rc =3D 0;=0A+ enum mcheck_type = rc =3D mcheck_none;=0A =0A switch (ci->x86) {=0A case 6:=0A@@ = -628,7 +628,9 @@ int mce_firstbank(struct cpuinfo_x86 *c)=0A /* This has = to be run for each processor */=0A void mcheck_init(struct cpuinfo_x86 = *c)=0A {=0A- int inited =3D 0, i, broadcast;=0A+ int i, broadcast;= =0A+ enum mcheck_type inited =3D mcheck_none;=0A+ static enum = mcheck_type g_type =3D mcheck_unset;=0A static int broadcast_check;=0A = =0A if (mce_disabled =3D=3D 1) {=0A@@ -694,9 +696,37 @@ void mcheck_ini= t(struct cpuinfo_x86 *c)=0A if (g_mcg_cap & MCG_CTL_P)=0A = rdmsrl(MSR_IA32_MCG_CTL, h_mcg_ctl);=0A set_poll_bankmask(c);=0A- if = (!inited)=0A- printk(XENLOG_INFO "CPU%i: No machine check = initialization\n",=0A- smp_processor_id());=0A+=0A+ if = (inited !=3D g_type) {=0A+ char prefix[20];=0A+ = static const char *const type_str[] =3D {=0A+ [mcheck_amd= _famXX] =3D "AMD",=0A+ [mcheck_amd_k7] =3D "AMD K7",=0A+ = [mcheck_amd_k8] =3D "AMD K8",=0A+ = [mcheck_intel] =3D "Intel"=0A+ };=0A+=0A+ snprintf(pr= efix, ARRAY_SIZE(prefix),=0A+ g_type !=3D mcheck_unset = ? XENLOG_WARNING "CPU%i: "=0A+ : = XENLOG_INFO,=0A+ smp_processor_id());=0A+ = BUG_ON(inited >=3D ARRAY_SIZE(type_str));=0A+ switch (inited) = {=0A+ default:=0A+ printk("%s%s machine check = reporting enabled\n",=0A+ prefix, type_str[ini= ted]);=0A+ break;=0A+ case mcheck_amd_fam= XX:=0A+ printk("%s%s Fam%xh machine check reporting = enabled\n",=0A+ prefix, type_str[inited], = c->x86);=0A+ break;=0A+ case mcheck_none:= =0A+ printk("%sNo machine check initialization\n", = prefix);=0A+ break;=0A+ }=0A+=0A+ = g_type =3D inited;=0A+ }=0A }=0A =0A u64 mce_cap_init(void)=0A--- = 2010-03-02.orig/xen/arch/x86/cpu/mcheck/mce.h 2010-03-16 16:18:34.0000000= 00 +0100=0A+++ 2010-03-02/xen/arch/x86/cpu/mcheck/mce.h 2010-03-16 = 09:25:22.000000000 +0100=0A@@ -28,13 +28,21 @@ extern int mce_verbosity;=0A= printk(s, ##a); \=0A } while (0)=0A =0A+enum = mcheck_type {=0A+ mcheck_unset =3D -1,=0A+ mcheck_none,=0A+ = mcheck_amd_famXX,=0A+ mcheck_amd_k7,=0A+ mcheck_amd_k8,=0A+ = mcheck_intel=0A+};=0A =0A /* Init functions */=0A-int amd_k7_mcheck_init(st= ruct cpuinfo_x86 *c);=0A-int amd_k8_mcheck_init(struct cpuinfo_x86 = *c);=0A-int amd_f10_mcheck_init(struct cpuinfo_x86 *c);=0A+enum mcheck_type= amd_k7_mcheck_init(struct cpuinfo_x86 *c);=0A+enum mcheck_type amd_k8_mche= ck_init(struct cpuinfo_x86 *c);=0A+enum mcheck_type amd_f10_mcheck_init(str= uct cpuinfo_x86 *c);=0A =0A-int intel_mcheck_init(struct cpuinfo_x86 = *c);=0A+enum mcheck_type intel_mcheck_init(struct cpuinfo_x86 *c);=0A =0A = void intel_mcheck_timer(struct cpuinfo_x86 *c);=0A void mce_intel_feature_i= nit(struct cpuinfo_x86 *c);=0A--- 2010-03-02.orig/xen/arch/x86/cpu/mcheck/m= ce_intel.c 2010-03-16 16:18:34.000000000 +0100=0A+++ 2010-03-02/xen/ar= ch/x86/cpu/mcheck/mce_intel.c 2010-03-16 17:11:44.000000000 +0100=0A@@ = -141,8 +141,9 @@ static void intel_init_thermal(struct cp=0A =0A l =3D = apic_read (APIC_LVTTHMR);=0A apic_write_around (APIC_LVTTHMR, l & = ~APIC_LVT_MASKED);=0A- printk (KERN_INFO "CPU%d: Thermal monitoring = enabled (%s)\n", =0A- cpu, tm2 ? "TM2" : "TM1");=0A+ if = (opt_cpu_info)=0A+ printk(KERN_INFO "CPU%u: Thermal monitoring = enabled (%s)\n",=0A+ cpu, tm2 ? "TM2" : "TM1");=0A = return;=0A }=0A #endif /* CONFIG_X86_MCE_THERMAL */=0A@@ -946,7 +947,8 @@ = static void intel_init_cmci(struct cpuin=0A int cpu =3D smp_processor_i= d();=0A =0A if (!mce_available(c) || !cmci_support) {=0A- = mce_printk(MCE_QUIET, "CMCI: CPU%d has no CMCI support\n", cpu);=0A+ = if (opt_cpu_info)=0A+ mce_printk(MCE_QUIET, "CMCI: CPU%d has = no CMCI support\n", cpu);=0A return;=0A }=0A =0A@@ -1068,11 = +1070,9 @@ static void mce_init(void)=0A }=0A =0A /* p4/p6 family have = similar MCA initialization process */=0A-int intel_mcheck_init(struct = cpuinfo_x86 *c)=0A+enum mcheck_type intel_mcheck_init(struct cpuinfo_x86 = *c)=0A {=0A _mce_cap_init(c);=0A- mce_printk(MCE_QUIET, "Intel = machine check reporting enabled on CPU#%d.\n",=0A- smp_processor= _id());=0A =0A /* machine check is available */=0A x86_mce_vector_r= egister(intel_machine_check);=0A@@ -1085,7 +1085,7 @@ int intel_mcheck_init= (struct cpuinfo_x86=0A mce_set_owner();=0A =0A open_softirq(MACHINE= _CHECK_SOFTIRQ, mce_softirq);=0A- return 1;=0A+ return mcheck_intel;= =0A }=0A =0A int intel_mce_wrmsr(uint32_t msr, uint64_t val)=0A--- = 2010-03-02.orig/xen/arch/x86/hvm/asid.c 2010-03-16 16:18:34.000000000 = +0100=0A+++ 2010-03-02/xen/arch/x86/hvm/asid.c 2010-03-15 17:41:13.0000000= 00 +0100=0A@@ -59,6 +59,7 @@ static DEFINE_PER_CPU(struct hvm_asid_da=0A = =0A void hvm_asid_init(int nasids)=0A {=0A+ static s8 g_disabled =3D = -1;=0A struct hvm_asid_data *data =3D &this_cpu(hvm_asid_data);=0A =0A = /*=0A@@ -72,8 +73,12 @@ void hvm_asid_init(int nasids)=0A = data->max_asid =3D nasids - 1;=0A data->disabled =3D (nasids <=3D = 1);=0A =0A- printk("HVM: ASIDs %s \n",=0A- (data->disabled ? = "disabled." : "enabled."));=0A+ if ( g_disabled !=3D data->disabled = )=0A+ {=0A+ printk("HVM: ASIDs %sabled.\n", data->disabled ? = "dis" : "en");=0A+ if ( g_disabled < 0 )=0A+ g_disabled = =3D data->disabled;=0A+ }=0A =0A /* Zero indicates 'invalid = generation', so we start the count at one. */=0A data->core_asid_genera= tion =3D 1;=0A--- 2010-03-02.orig/xen/arch/x86/setup.c 2010-03-16 = 16:18:34.000000000 +0100=0A+++ 2010-03-02/xen/arch/x86/setup.c 2010-03-16 = 10:55:07.000000000 +0100=0A@@ -269,8 +269,8 @@ void __devinit srat_detect_n= ode(int cpu)=0A node =3D 0;=0A numa_set_node(cpu, node);=0A = =0A- if ( acpi_numa > 0 )=0A- printk(KERN_INFO "CPU %d APIC %d = -> Node %d\n", cpu, apicid, node);=0A+ if ( opt_cpu_info && acpi_numa > = 0 )=0A+ printk("CPU %d APIC %d -> Node %d\n", cpu, apicid, = node);=0A }=0A =0A /*=0A--- 2010-03-02.orig/xen/arch/x86/smpboot.c = 2010-03-16 16:18:34.000000000 +0100=0A+++ 2010-03-02/xen/arch/x86/smpboot.c= 2010-03-16 09:16:52.000000000 +0100=0A@@ -877,7 +877,9 @@ static = int __devinit do_boot_cpu(int api=0A start_eip =3D setup_trampoline();= =0A =0A /* So we see what's up */=0A- printk("Booting processor = %d/%d eip %lx\n", cpu, apicid, start_eip);=0A+ if (opt_cpu_info)=0A+ = printk("Booting processor %d/%d eip %lx\n",=0A+ cpu, = apicid, start_eip);=0A =0A stack_start.esp =3D prepare_idle_stack(cpu)= ;=0A =0A@@ -960,8 +962,7 @@ static int __devinit do_boot_cpu(int api=0A = if (cpu_isset(cpu, cpu_callin_map)) {=0A /* = number CPUs logically, starting from 1 (BSP is 0) */=0A = Dprintk("OK.\n");=0A- printk("CPU%d: ", cpu);=0A- = print_cpu_info(&cpu_data[cpu]);=0A+ print_cpu_i= nfo(cpu);=0A Dprintk("CPU has booted.\n");=0A = } else {=0A boot_error =3D 1;=0A@@ -1062,8 +1063,7 @@ = static void __init smp_boot_cpus(unsigne=0A * Setup boot CPU = information=0A */=0A smp_store_cpu_info(0); /* Final full version of = the data */=0A- printk("CPU%d: ", 0);=0A- print_cpu_info(&cpu_data[0]= );=0A+ print_cpu_info(0);=0A =0A boot_cpu_physical_apicid =3D = get_apic_id();=0A x86_cpu_to_apicid[0] =3D boot_cpu_physical_apicid;= =0A--- 2010-03-02.orig/xen/drivers/char/console.c 2010-03-16 = 16:18:39.000000000 +0100=0A+++ 2010-03-02/xen/drivers/char/console.c = 2010-03-16 16:41:10.000000000 +0100=0A@@ -65,7 +65,12 @@ size_param("conrin= g_size", opt_conring_s=0A =0A #define _CONRING_SIZE 16384=0A #define = CONRING_IDX_MASK(i) ((i)&(conring_size-1))=0A-static char _conring[_CONRING= _SIZE], *__read_mostly conring =3D _conring;=0A+static char=0A+#if = _CONRING_SIZE >=3D PAGE_SIZE=0A+ __attribute__((__section__(".bss.page_a= ligned"), __aligned__(PAGE_SIZE)))=0A+#endif=0A+ _conring[_CONRING_SIZE]= ;=0A+static char *__read_mostly conring =3D _conring;=0A static uint32_t = __read_mostly conring_size =3D _CONRING_SIZE;=0A static uint32_t conringc, = conringp;=0A =0A@@ -595,6 +600,8 @@ void __init console_init_postirq(void)= =0A =0A serial_init_postirq();=0A =0A+ if ( !opt_conring_size )=0A+ = opt_conring_size =3D num_present_cpus() << (9 + xenlog_lower_thresh)= ;=0A /* Round size down to a power of two. */=0A while ( opt_conrin= g_size & (opt_conring_size - 1) )=0A opt_conring_size &=3D = opt_conring_size - 1;=0A@@ -618,6 +625,8 @@ void __init console_init_postir= q(void)=0A spin_unlock_irq(&console_lock);=0A =0A printk("Allocated= console ring of %u KiB.\n", opt_conring_size >> 10);=0A+=0A+ init_xenhe= ap_pages(__pa(_conring), __pa(_conring + _CONRING_SIZE));=0A }=0A =0A void = __init console_endboot(void)=0A--- 2010-03-02.orig/xen/include/asm-x86/proc= essor.h 2010-03-16 16:18:34.000000000 +0100=0A+++ 2010-03-02/xen/include/as= m-x86/processor.h 2010-03-15 17:55:08.000000000 +0100=0A@@ -194,10 = +194,11 @@ extern struct cpuinfo_x86 cpu_data[];=0A extern u64 host_pat;=0A= extern int phys_proc_id[NR_CPUS];=0A extern int cpu_core_id[NR_CPUS];=0A+e= xtern int opt_cpu_info;=0A =0A extern void identify_cpu(struct cpuinfo_x86 = *);=0A extern void setup_clear_cpu_cap(unsigned int);=0A-extern void = print_cpu_info(struct cpuinfo_x86 *);=0A+extern void print_cpu_info(unsigne= d int cpu);=0A extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 = *c);=0A extern void dodgy_tsc(void);=0A =0A --=__Part406A994D.0__= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel --=__Part406A994D.0__=--