From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Jan Beulich" Subject: [PATCH] x86: add support for domain initiated global cache flush Date: Thu, 29 Apr 2010 16:59:49 +0100 Message-ID: <4BD9C9150200007800000B14@vpn.id2.novell.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="=__PartB3992CE5.0__=" Return-path: List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: xen-devel@lists.xensource.com List-Id: xen-devel@lists.xenproject.org This is a MIME message. If you are reading this text, you may want to consider changing to a mail reader or gateway that understands how to properly handle MIME multipart messages. --=__PartB3992CE5.0__= Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Content-Disposition: inline Newer Linux' AGP code wants to flush caches on all CPUs under certain circumstances. Since doing this on all vCPU-s of the domain in question doesn't yield the intended effect, this needs to be done in the hypervisor. Add a new MMUEXT operation for this. While looking at the pre-existing flush implementation, I also noticed an off-by-one error in the cache flush portion of flush_area_local(). Signed-off-by: Jan Beulich --- 2010-04-22.orig/xen/arch/x86/flushtlb.c 2008-10-14 19:44:12.0000000= 00 +0200 +++ 2010-04-22/xen/arch/x86/flushtlb.c 2010-04-29 17:47:22.000000000 = +0200 @@ -149,7 +149,7 @@ void flush_area_local(const void *va, un { unsigned long i, sz =3D 0; =20 - if ( order < (BITS_PER_LONG - PAGE_SHIFT - 1) ) + if ( order < (BITS_PER_LONG - PAGE_SHIFT) ) sz =3D 1UL << (order + PAGE_SHIFT); =20 if ( c->x86_clflush_size && c->x86_cache_size && sz && --- 2010-04-22.orig/xen/arch/x86/mm.c 2010-04-29 17:35:20.000000000 = +0200 +++ 2010-04-22/xen/arch/x86/mm.c 2010-04-29 17:51:08.000000000 = +0200 @@ -2889,6 +2889,27 @@ int do_mmuext_op( } break; =20 + case MMUEXT_FLUSH_CACHE_GLOBAL: + if ( unlikely(foreigndom !=3D DOMID_SELF) ) + okay =3D 0; + else if ( likely(cache_flush_permitted(d)) ) + { + unsigned int cpu; + cpumask_t mask =3D CPU_MASK_NONE; + + for_each_online_cpu(cpu) + if ( !cpus_intersects(mask, + per_cpu(cpu_sibling_map, cpu)) = ) + cpu_set(cpu, mask); + flush_mask(&mask, FLUSH_CACHE); + } + else + { + MEM_LOG("Non-physdev domain tried to FLUSH_CACHE_GLOBAL");= + okay =3D 0; + } + break; + case MMUEXT_SET_LDT: { unsigned long ptr =3D op.arg1.linear_addr; --- 2010-04-22.orig/xen/include/public/xen.h 2010-04-29 17:35:20.0000000= 00 +0200 +++ 2010-04-22/xen/include/public/xen.h 2010-04-29 17:09:30.000000000 = +0200 @@ -239,6 +239,10 @@ DEFINE_XEN_GUEST_HANDLE(xen_pfn_t); *=20 * cmd: MMUEXT_FLUSH_CACHE * No additional arguments. Writes back and flushes cache contents. + * + * cmd: MMUEXT_FLUSH_CACHE_GLOBAL + * No additional arguments. Writes back and flushes cache contents + * on all CPUs in the system. *=20 * cmd: MMUEXT_SET_LDT * linear_addr: Linear address of LDT base (NB. must be page-aligned). @@ -268,6 +272,7 @@ DEFINE_XEN_GUEST_HANDLE(xen_pfn_t); #define MMUEXT_NEW_USER_BASEPTR 15 #define MMUEXT_CLEAR_PAGE 16 #define MMUEXT_COPY_PAGE 17 +#define MMUEXT_FLUSH_CACHE_GLOBAL 18 =20 #ifndef __ASSEMBLY__ struct mmuext_op { --=__PartB3992CE5.0__= Content-Type: text/plain; name="x86-cache-flush-global.patch" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="x86-cache-flush-global.patch" Newer Linux' AGP code wants to flush caches on all CPUs under certain=0Acir= cumstances. Since doing this on all vCPU-s of the domain in=0Aquestion = doesn't yield the intended effect, this needs to be done in=0Athe = hypervisor. Add a new MMUEXT operation for this.=0A=0AWhile looking at the = pre-existing flush implementation, I also noticed=0Aan off-by-one error in = the cache flush portion of flush_area_local().=0A=0ASigned-off-by: Jan = Beulich =0A=0A--- 2010-04-22.orig/xen/arch/x86/flushtl= b.c 2008-10-14 19:44:12.000000000 +0200=0A+++ 2010-04-22/xen/arch/x86/f= lushtlb.c 2010-04-29 17:47:22.000000000 +0200=0A@@ -149,7 +149,7 @@ = void flush_area_local(const void *va, un=0A {=0A unsigned long = i, sz =3D 0;=0A =0A- if ( order < (BITS_PER_LONG - PAGE_SHIFT - 1) = )=0A+ if ( order < (BITS_PER_LONG - PAGE_SHIFT) )=0A sz = =3D 1UL << (order + PAGE_SHIFT);=0A =0A if ( c->x86_clflush_size = && c->x86_cache_size && sz &&=0A--- 2010-04-22.orig/xen/arch/x86/mm.c = 2010-04-29 17:35:20.000000000 +0200=0A+++ 2010-04-22/xen/arch/x86/mm.c = 2010-04-29 17:51:08.000000000 +0200=0A@@ -2889,6 +2889,27 @@ int do_mmuext_= op(=0A }=0A break;=0A =0A+ case MMUEXT_FLUSH= _CACHE_GLOBAL:=0A+ if ( unlikely(foreigndom !=3D DOMID_SELF) = )=0A+ okay =3D 0;=0A+ else if ( likely(cache_flus= h_permitted(d)) )=0A+ {=0A+ unsigned int = cpu;=0A+ cpumask_t mask =3D CPU_MASK_NONE;=0A+=0A+ = for_each_online_cpu(cpu)=0A+ if ( !cpus_intersects= (mask,=0A+ per_cpu(cpu_sibling_map= , cpu)) )=0A+ cpu_set(cpu, mask);=0A+ = flush_mask(&mask, FLUSH_CACHE);=0A+ }=0A+ else=0A+ = {=0A+ MEM_LOG("Non-physdev domain tried to = FLUSH_CACHE_GLOBAL");=0A+ okay =3D 0;=0A+ }=0A+ = break;=0A+=0A case MMUEXT_SET_LDT:=0A {=0A = unsigned long ptr =3D op.arg1.linear_addr;=0A--- 2010-04-22.orig/xen= /include/public/xen.h 2010-04-29 17:35:20.000000000 +0200=0A+++ = 2010-04-22/xen/include/public/xen.h 2010-04-29 17:09:30.000000000 = +0200=0A@@ -239,6 +239,10 @@ DEFINE_XEN_GUEST_HANDLE(xen_pfn_t);=0A * =0A = * cmd: MMUEXT_FLUSH_CACHE=0A * No additional arguments. Writes back and = flushes cache contents.=0A+ *=0A+ * cmd: MMUEXT_FLUSH_CACHE_GLOBAL=0A+ * = No additional arguments. Writes back and flushes cache contents=0A+ * on = all CPUs in the system.=0A * =0A * cmd: MMUEXT_SET_LDT=0A * linear_addr:= Linear address of LDT base (NB. must be page-aligned).=0A@@ -268,6 +272,7 = @@ DEFINE_XEN_GUEST_HANDLE(xen_pfn_t);=0A #define MMUEXT_NEW_USER_BASEPTR = 15=0A #define MMUEXT_CLEAR_PAGE 16=0A #define MMUEXT_COPY_PAGE = 17=0A+#define MMUEXT_FLUSH_CACHE_GLOBAL 18=0A =0A #ifndef __ASSEMBLY__=0A = struct mmuext_op {=0A --=__PartB3992CE5.0__= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel --=__PartB3992CE5.0__=--