From: "Jan Beulich" <JBeulich@novell.com>
To: Jun Nakajima <jun.nakajima@intel.com>,
Liping Ke <liping.ke@intel.com>, Xin Li <xin.li@intel.com>
Cc: xen-devel@lists.xensource.com, Keir Fraser <keir.fraser@eu.citrix.com>
Subject: Re: [patch] x86: Add CPU Feature Mask support (cpu spoof) for NHM
Date: Tue, 15 Jun 2010 08:50:02 +0100 [thread overview]
Message-ID: <4C174CCB0200007800006719@vpn.id2.novell.com> (raw)
In-Reply-To: <789F9655DD1B8F43B48D77C5D30659731E84D241@shsmsx501.ccr.corp.intel.com>
>>> On 04.06.10 at 04:57, "Ke, Liping" <liping.ke@intel.com> wrote:
> This is a small patch for adding cpu feature mask feature for
> NHMs. This patch has been tested under several types of CPUs.
This isn't fully consistent with the just released documentation:
- for model 0x17, you reject steppings below 4 (doc says all steppings qualify)
- for model 0x1a, you reject steppings up to 2 (doc says all steppings qualify)
- you don't allow model 0x1f at all (doc says it qualifies)
In a patch I'll submit (presumably) later today I'll leave the stepping
handling as is, but include model 0x1f as per the documentation. It
would be nice if you could clarify matters.
Thanks, Jan
prev parent reply other threads:[~2010-06-15 7:50 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-06-04 2:57 [patch] x86: Add CPU Feature Mask support (cpu spoof) for NHM Ke, Liping
2010-06-15 7:50 ` Jan Beulich [this message]
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