[patch] x86: Add CPU Feature Mask support (cpu spoof) for NHM

[patch] x86: Add CPU Feature Mask support (cpu spoof) for NHM

[Ke, Liping]

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Hi, Keir

This is a small patch for adding cpu feature mask feature for 
NHMs. This patch has been tested under several types of CPUs.

Any problem, just let me know.

Thanks & Regards,
criping


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Add CPUID feature mask support for NHM in XEN.

Signed-off-by: Jun Nakajima <jun.nakajima@intel.com>
Signed-off-by: Liping Ke <liping.ke@intel.com>
diff -r 4ab68bf4c37e xen/arch/x86/cpu/intel.c
--- a/xen/arch/x86/cpu/intel.c	Thu Jun 03 07:30:54 2010 +0100
+++ b/xen/arch/x86/cpu/intel.c	Fri Jun 04 10:46:20 2010 +0800
@@ -29,6 +29,9 @@ static unsigned int opt_cpuid_mask_ecx, 
 static unsigned int opt_cpuid_mask_ecx, opt_cpuid_mask_edx;
 integer_param("cpuid_mask_ecx", opt_cpuid_mask_ecx);
 integer_param("cpuid_mask_edx", opt_cpuid_mask_edx);
+static unsigned int opt_cpuid_mask_ext_ecx, opt_cpuid_mask_ext_edx;
+integer_param("cpuid_mask_ext_ecx", opt_cpuid_mask_ext_ecx);
+integer_param("cpuid_mask_ext_edx", opt_cpuid_mask_ext_edx);
 
 static int use_xsave = 1;
 boolean_param("xsave", use_xsave);
@@ -40,24 +43,46 @@ struct movsl_mask movsl_mask __read_most
 struct movsl_mask movsl_mask __read_mostly;
 #endif
 
-static void __devinit set_cpuidmask(void)
-{
-	unsigned int eax, ebx, ecx, edx, model;
-
-	if (!(opt_cpuid_mask_ecx | opt_cpuid_mask_edx))
-		return;
-
-	cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
-	model = ((eax & 0xf0000) >> 12) | ((eax & 0xf0) >> 4);
-	if (!((model == 0x1d) || ((model == 0x17) && ((eax & 0xf) >= 4)))) {
+static void __devinit set_cpuidmask(struct cpuinfo_x86 *c)
+{
+	unsigned int model = c->x86_model;
+
+	if (!(opt_cpuid_mask_ecx | opt_cpuid_mask_edx | 
+	      opt_cpuid_mask_ext_ecx | opt_cpuid_mask_ext_edx))
+		return;
+
+	if (c->x86 != 0x6)	/* Only family 6 supports this feature  */
+		return;
+
+	if ((model == 0x1d) || ((model == 0x17) && (c->x86_mask >= 4))) {
+		wrmsr(MSR_IA32_CPUID_FEATURE_MASK1,
+		      opt_cpuid_mask_ecx ? : ~0u,
+		      opt_cpuid_mask_edx ? : ~0u);
+	}
+/* 
+ * CPU supports this feature if the processor signature meets the following:
+ * (CPUID.(EAX=01h):EAX) > 000106A2h, or
+ * (CPUID.(EAX=01h):EAX) == 000106Exh, 0002065xh, 000206Cxh, 000206Exh, or 000206Fxh
+ *
+ */
+	else if (((model == 0x1a) && (c->x86_mask > 2))
+		 || model == 0x1e
+		 || model == 0x25 
+		 || model == 0x2c 
+		 || model == 0x2e 
+		 || model == 0x2f) {
+		wrmsr(MSR_IA32_CPUID1_FEATURE_MASK,
+		      opt_cpuid_mask_ecx ? : ~0u,
+		      opt_cpuid_mask_edx ? : ~0u);
+		wrmsr(MSR_IA32_CPUID80000001_FEATURE_MASK,
+		      opt_cpuid_mask_ext_ecx ? : ~0u,
+		      opt_cpuid_mask_ext_edx ? : ~0u);
+	}
+	else {
 		printk(XENLOG_ERR "Cannot set CPU feature mask on CPU#%d\n",
 		       smp_processor_id());
 		return;
 	}
-
-	wrmsr(MSR_IA32_CPUID_FEATURE_MASK1,
-	      opt_cpuid_mask_ecx ? : ~0u,
-	      opt_cpuid_mask_edx ? : ~0u);
 }
 
 void __devinit early_intel_workaround(struct cpuinfo_x86 *c)
@@ -179,7 +204,7 @@ static void __devinit init_intel(struct 
 
 	detect_ht(c);
 
-	set_cpuidmask();
+	set_cpuidmask(c);
 
 	/* Work around errata */
 	Intel_errata_workarounds(c);
diff -r 4ab68bf4c37e xen/include/asm-x86/msr-index.h
--- a/xen/include/asm-x86/msr-index.h	Thu Jun 03 07:30:54 2010 +0100
+++ b/xen/include/asm-x86/msr-index.h	Fri Jun 04 10:46:20 2010 +0800
@@ -158,6 +158,8 @@
 
 /* MSR for cpuid feature mask */
 #define MSR_IA32_CPUID_FEATURE_MASK1	0x00000478
+#define MSR_IA32_CPUID1_FEATURE_MASK    0x00000130
+#define MSR_IA32_CPUID80000001_FEATURE_MASK 0x00000131
 
 /* MSRs & bits used for VMX enabling */
 #define MSR_IA32_VMX_BASIC                      0x480

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Re: [patch] x86: Add CPU Feature Mask support (cpu spoof) for NHM

[Jan Beulich]

>>> On 04.06.10 at 04:57, "Ke, Liping" <liping.ke@intel.com> wrote:
> This is a small patch for adding cpu feature mask feature for 
> NHMs. This patch has been tested under several types of CPUs.

This isn't fully consistent with the just released documentation:

- for model 0x17, you reject steppings below 4 (doc says all steppings qualify)
- for model 0x1a, you reject steppings up to 2 (doc says all steppings qualify)
- you don't allow model 0x1f at all (doc says it qualifies)

In a patch I'll submit (presumably) later today I'll leave the stepping
handling as is, but include model 0x1f as per the documentation. It
would be nice if you could clarify matters.

Thanks, Jan