From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Jan Beulich" Subject: [PATCH] x86/mce: assorted fixes Date: Tue, 15 Jun 2010 13:11:08 +0100 Message-ID: <4C1789FC02000078000067C7@vpn.id2.novell.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="=__Part92BFC4CC.0__=" Return-path: List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: xen-devel@lists.xensource.com List-Id: xen-devel@lists.xenproject.org This is a MIME message. If you are reading this text, you may want to consider changing to a mail reader or gateway that understands how to properly handle MIME multipart messages. --=__Part92BFC4CC.0__= Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Content-Disposition: inline - correct various range checks (avoids bogus warnings on domains modifying virtualized MSRs) - correct consistency check (so that APs get checked instead of the BP [against uninitialized data]) - reduce verbosity (capabilities printed only once, but then all of the relevant values) Signed-off-by: Jan Beulich --- 2010-06-15.orig/xen/arch/x86/cpu/mcheck/mce.h 2010-06-14 = 08:49:36.000000000 +0200 +++ 2010-06-15/xen/arch/x86/cpu/mcheck/mce.h 2010-06-15 12:06:59.0000000= 00 +0200 @@ -173,15 +173,14 @@ extern unsigned int nr_mce_banks; static inline int mce_vendor_bank_msr(uint32_t msr) { if ( boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL && - (msr > MSR_IA32_MC0_CTL2 && msr < (MSR_IA32_MC0_CTL2 + nr_mce_bank= s)) ) + msr >=3D MSR_IA32_MC0_CTL2 && msr < (MSR_IA32_MC0_CTL2 + = nr_mce_banks) ) return 1; return 0; } =20 static inline int mce_bank_msr(uint32_t msr) { - if ( (msr > MSR_IA32_MC0_CTL2 && - msr < (MSR_IA32_MCx_CTL(nr_mce_banks - 1))) || + if ( (msr >=3D MSR_IA32_MC0_CTL && msr < MSR_IA32_MCx_CTL(nr_mce_banks= )) || mce_vendor_bank_msr(msr) ) return 1; return 0; --- 2010-06-15.orig/xen/arch/x86/cpu/mcheck/mce_intel.c 2010-06-14 = 08:49:36.000000000 +0200 +++ 2010-06-15/xen/arch/x86/cpu/mcheck/mce_intel.c 2010-06-15 = 12:08:53.000000000 +0200 @@ -1145,26 +1145,26 @@ static void intel_init_mca(struct cpuinf =20 first =3D mce_firstbank(c); =20 - dprintk(XENLOG_INFO, "MCA Capaility: CPU %x SER %x" - "CMCI %x firstbank %x extended MCE MSR %x\n", - smp_processor_id(), ser, cmci, first, ext_num); - - if (smp_processor_id()) + if (smp_processor_id() =3D=3D 0) { + dprintk(XENLOG_INFO, "MCA Capability: BCAST %x SER %x" + " CMCI %x firstbank %x extended MCE MSR %x\n", + broadcast, ser, cmci, first, ext_num); + mce_broadcast =3D broadcast; cmci_support =3D cmci; ser_support =3D ser; nr_intel_ext_msrs =3D ext_num; firstbank =3D first; } - else - { - if (cmci !=3D cmci_support || ser !=3D ser_support || - broadcast !=3D mce_broadcast || - first !=3D firstbank) - dprintk(XENLOG_WARNING, - "CPU %x has different MCA capability with BSP\n" - "may cause undetermined result!!!\n", smp_processor_id()); + else if (cmci !=3D cmci_support || ser !=3D ser_support || + broadcast !=3D mce_broadcast || + first !=3D firstbank || ext_num !=3D nr_intel_ext_msrs) + { + dprintk(XENLOG_WARNING, + "CPU %u has different MCA capability (%x,%x,%x,%x,%x)" + " than BSP, may cause undetermined result!!!\n", + smp_processor_id(), broadcast, ser, cmci, first, = ext_num); } } =20 @@ -1264,8 +1264,7 @@ int intel_mce_wrmsr(uint32_t msr, uint64 { int ret =3D 0; =20 - if (msr > MSR_IA32_MC0_CTL2 && - msr < (MSR_IA32_MC0_CTL2 + nr_mce_banks - 1)) + if (msr >=3D MSR_IA32_MC0_CTL2 && msr < (MSR_IA32_MC0_CTL2 + = nr_mce_banks)) { mce_printk(MCE_QUIET, "We have disabled CMCI capability, " "Guest should not write this MSR!\n"); @@ -1279,8 +1278,7 @@ int intel_mce_rdmsr(uint32_t msr, uint64 { int ret =3D 0; =20 - if (msr > MSR_IA32_MC0_CTL2 && - msr < (MSR_IA32_MC0_CTL2 + nr_mce_banks - 1)) + if (msr >=3D MSR_IA32_MC0_CTL2 && msr < (MSR_IA32_MC0_CTL2 + = nr_mce_banks)) { mce_printk(MCE_QUIET, "We have disabled CMCI capability, " "Guest should not read this MSR!\n"); --=__Part92BFC4CC.0__= Content-Type: text/plain; name="x86-mce-intel.patch" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="x86-mce-intel.patch" - correct various range checks (avoids bogus warnings on domains=0A = modifying virtualized MSRs)=0A- correct consistency check (so that APs get = checked instead of the=0A BP [against uninitialized data])=0A- reduce = verbosity (capabilities printed only once, but then all of=0A the = relevant values)=0A=0ASigned-off-by: Jan Beulich =0A= =0A--- 2010-06-15.orig/xen/arch/x86/cpu/mcheck/mce.h 2010-06-14 = 08:49:36.000000000 +0200=0A+++ 2010-06-15/xen/arch/x86/cpu/mcheck/mce.h = 2010-06-15 12:06:59.000000000 +0200=0A@@ -173,15 +173,14 @@ extern = unsigned int nr_mce_banks;=0A static inline int mce_vendor_bank_msr(uint32_= t msr)=0A {=0A if ( boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL = &&=0A- (msr > MSR_IA32_MC0_CTL2 && msr < (MSR_IA32_MC0_CTL2 + = nr_mce_banks)) )=0A+ msr >=3D MSR_IA32_MC0_CTL2 && msr < (MSR_IA32_= MC0_CTL2 + nr_mce_banks) )=0A return 1;=0A return 0;=0A }=0A = =0A static inline int mce_bank_msr(uint32_t msr)=0A {=0A- if ( (msr > = MSR_IA32_MC0_CTL2 &&=0A- msr < (MSR_IA32_MCx_CTL(nr_mce_banks - = 1))) ||=0A+ if ( (msr >=3D MSR_IA32_MC0_CTL && msr < MSR_IA32_MCx_CTL(nr= _mce_banks)) ||=0A mce_vendor_bank_msr(msr) )=0A return = 1;=0A return 0;=0A--- 2010-06-15.orig/xen/arch/x86/cpu/mcheck/mce_intel= .c 2010-06-14 08:49:36.000000000 +0200=0A+++ 2010-06-15/xen/arch/x86/c= pu/mcheck/mce_intel.c 2010-06-15 12:08:53.000000000 +0200=0A@@ -1145,26 = +1145,26 @@ static void intel_init_mca(struct cpuinf=0A =0A first =3D = mce_firstbank(c);=0A =0A- dprintk(XENLOG_INFO, "MCA Capaility: CPU %x = SER %x"=0A- "CMCI %x firstbank %x extended MCE MSR %x\n",=0A- = smp_processor_id(), ser, cmci, first, ext_num);=0A-=0A- if (smp_processo= r_id())=0A+ if (smp_processor_id() =3D=3D 0)=0A {=0A+ = dprintk(XENLOG_INFO, "MCA Capability: BCAST %x SER %x"=0A+ = " CMCI %x firstbank %x extended MCE MSR %x\n",=0A+ = broadcast, ser, cmci, first, ext_num);=0A+=0A mce_broadcast =3D = broadcast;=0A cmci_support =3D cmci;=0A ser_support =3D = ser;=0A nr_intel_ext_msrs =3D ext_num;=0A firstbank =3D = first;=0A }=0A- else=0A- {=0A- if (cmci !=3D cmci_support = || ser !=3D ser_support ||=0A- broadcast !=3D mce_broadcast = ||=0A- first !=3D firstbank)=0A- dprintk(XENLOG_WARNI= NG,=0A- "CPU %x has different MCA capability with BSP\n"=0A- = "may cause undetermined result!!!\n", smp_processor_id());=0A+ = else if (cmci !=3D cmci_support || ser !=3D ser_support ||=0A+ = broadcast !=3D mce_broadcast ||=0A+ first !=3D firstbank || = ext_num !=3D nr_intel_ext_msrs)=0A+ {=0A+ dprintk(XENLOG_WARNING,= =0A+ "CPU %u has different MCA capability (%x,%x,%x,%x,%x)"= =0A+ " than BSP, may cause undetermined result!!!\n",=0A+ = smp_processor_id(), broadcast, ser, cmci, first, ext_num);=0A = }=0A }=0A =0A@@ -1264,8 +1264,7 @@ int intel_mce_wrmsr(uint32_t msr, = uint64=0A {=0A int ret =3D 0;=0A =0A- if (msr > MSR_IA32_MC0_CTL2 = &&=0A- msr < (MSR_IA32_MC0_CTL2 + nr_mce_banks - 1))=0A+ if (msr = >=3D MSR_IA32_MC0_CTL2 && msr < (MSR_IA32_MC0_CTL2 + nr_mce_banks))=0A = {=0A mce_printk(MCE_QUIET, "We have disabled CMCI capability, "=0A = "Guest should not write this MSR!\n");=0A@@ -1279,8 = +1278,7 @@ int intel_mce_rdmsr(uint32_t msr, uint64=0A {=0A int ret = =3D 0;=0A =0A- if (msr > MSR_IA32_MC0_CTL2 &&=0A- msr < = (MSR_IA32_MC0_CTL2 + nr_mce_banks - 1))=0A+ if (msr >=3D MSR_IA32_MC0_CT= L2 && msr < (MSR_IA32_MC0_CTL2 + nr_mce_banks))=0A {=0A = mce_printk(MCE_QUIET, "We have disabled CMCI capability, "=0A = "Guest should not read this MSR!\n");=0A --=__Part92BFC4CC.0__= Content-Type: text/plain; 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