xen-devel.lists.xenproject.org archive mirror
 help / color / mirror / Atom feed
* [PATCH] C6 state with EOI issue fix for some Intel processors
@ 2010-09-15  7:10 Sheng Yang
  2010-09-15  7:18 ` Sheng Yang
                   ` (2 more replies)
  0 siblings, 3 replies; 6+ messages in thread
From: Sheng Yang @ 2010-09-15  7:10 UTC (permalink / raw)
  To: Keir Fraser; +Cc: xen-devel@lists.xensource.com

[-- Attachment #1: Type: Text/Plain, Size: 583 bytes --]

There is an errata in some of Intel processors.

AAJ72. EOI Transaction May Not be Sent if Software Enters Core C6 During
an Interrupt Service Routine

If core C6 is entered after the start of an interrupt service routine but before
a write to the APIC EOI register, the core may not send an EOI transaction (if
needed) and further interrupts from the same priority level or lower may be
blocked.

This patch fix this issue, by checking if ISR is pending before enter deep Cx 
state. If so, it would use power->safe_state instead of deep Cx state to prevent 
the above issue happen.

[-- Attachment #2: c6_eoi_fix.patch --]
[-- Type: text/x-patch, Size: 1429 bytes --]

diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c
--- a/xen/arch/x86/acpi/cpu_idle.c
+++ b/xen/arch/x86/acpi/cpu_idle.c
@@ -367,6 +367,28 @@
     return atomic_read(&this_cpu(schedule_data).urgent_count);
 }
 
+static int cpu_has_isr_pending(void)
+{
+    int i;
+
+    for ( i = 1; i < 8; i++ )
+        if ( apic_read(APIC_ISR + (i << 4)) != 0 )
+            return 1;
+    return 0;
+}
+
+int errata_c6_eoi_fix_needed(void)
+{
+    int model = boot_cpu_data.x86_model;
+    if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
+            boot_cpu_data.x86 == 6 &&
+            ((model == 0x1a || model == 0x1e || model == 0x1f ||
+	     model == 0x25 || model == 0x2c || model == 0x2f) &&
+              !directed_eoi_enabled) )
+        return 1;
+    return 0;
+}
+
 static void acpi_processor_idle(void)
 {
     struct acpi_processor_power *power = processor_powers[smp_processor_id()];
@@ -417,6 +439,16 @@
         return;
     }
 
+    /*
+     * There was an errata with some Core i7 processors that, EOI
+     * transaction may not be sent if software enters core C6 during an
+     * interrupt service routine. So we don't want to get into deep Cx
+     * state if there was isr pending.
+     */
+    if ( cpu_has_apic && errata_c6_eoi_fix_needed() &&
+           cx->type == ACPI_STATE_C3 && cpu_has_isr_pending() )
+        cx = power->safe_state;
+
     power->last_state = cx;
 
     /*

[-- Attachment #3: Type: text/plain, Size: 138 bytes --]

_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xensource.com
http://lists.xensource.com/xen-devel

^ permalink raw reply	[flat|nested] 6+ messages in thread
end of thread, other threads:[~2010-09-16  0:23 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2010-09-15  7:10 [PATCH] C6 state with EOI issue fix for some Intel processors Sheng Yang
2010-09-15  7:18 ` Sheng Yang
2010-09-15  7:32 ` Keir Fraser
2010-09-15  8:03 ` Keir Fraser
2010-09-15 13:42   ` Andreas Kinzler
2010-09-16  0:23     ` Sheng Yang

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).