From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andre Przywara Subject: [PATCH 0/5 -v3] xl: add cpuid config file option Date: Thu, 16 Sep 2010 15:04:36 +0200 Message-ID: <4C9215E4.7070302@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset="ISO-8859-1"; format=flowed Content-Transfer-Encoding: 7bit Return-path: List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: Stefano Stabellini , Ian Campbell Cc: xen-devel , Keir Fraser List-Id: xen-devel@lists.xenproject.org Hi, again an updated version of the patch series to introduce a cpuid parameter in xl. Changes from v2: - fix the IDL part to use pass-by-reference and to make the type opaque - use strtok_r instead of strtok to avoid interference with other strtoks. - fix 3DNow bit numbers (swapped 3dnow and 3dnowext) - fix bug with cpuid="" - fix bug with comparison of flag names - make one error message more verbose Hope that this is the final version. Regards, Andre. -------------- xl is currently ignoring the cpuid= variable in the config file. As I don't like the current interface xm exposes (basically because it is complicated, unintuitive and very error prone), I implemented a new scheme for specifying CPUID flags policy, combining QEMU's and Xen's approach: cpuid = ",=[01xks]*,... The patch includes a (preliminary) list of feature names along with their bit positions. The value for each feature bit copies the current meaning is Xen: 0: clear, 1: set, x: don't care/use default, k: keep from host, s: use host but preserve across migration The value can also be a number (either in hex or decimal), so things like "stepping=3" can be easily specified. To show you the advantage, I quote the example config file: > #cpuid=[ '1:ecx=xxxxxxxxxxx00xxxxxxxxxxxxxxxxxxx, > # eax=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' ] > # - Unset the SSE4 features (CPUID.1[ECX][20-19]) > # - Default behaviour for all other bits in ECX And EAX registers. new version: cpuid = "host,sse4.1=0,sse4.2=0" > # Expose to the guest multi-core cpu instead of multiple processors > # Example for intel, expose a 8-core processor : > #cpuid=['1:edx=xxx1xxxxxxxxxxxxxxxxxxxxxxxxxxxx, > # ebx=xxxxxxxx00010000xxxxxxxxxxxxxxxx', > # '4,0:eax=001111xxxxxxxxxxxxxxxxxxxxxxxxxx'] > # - CPUID.1[EDX][HT] : Enable HT > # - CPUID.1[EBX] : Number of vcpus * 2 > # - CPUID.4,0[EAX] : Number of vcpus * 2 - 1 > #vcpus=8 new version: cpuid = "host,htt=1,proccount=16,maxcores=15" > # Example for amd, expose a 5-core processor : > # cpuid = ['1:ebx=xxxxxxxx00001010xxxxxxxxxxxxxxxx, > # edx=xxx1xxxxxxxxxxxxxxxxxxxxxxxxxxxx', > # '0x80000001:ecx=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1x', > # '0x80000008:ecx=xxxxxxxxxxxxxxxxxxxxxxxxxx001001'] > # - CPUID.1[EBX] : Threads per Core * Cores per Socket (2 * #vcpus) > # - CPUID.1[EDX][HT] : Enable HT > # - CPUID.0x80000001[CmpLegacy] : Use legacy method > # - CPUID.0x80000008[ECX] : #vcpus * 2 - 1 new version: cpuid="host,htt=1,cmplegacy=1,proccount=10,nc=9" -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 448-3567-12