From mboxrd@z Thu Jan  1 00:00:00 1970
From: "Jan Beulich" <JBeulich@novell.com>
Subject: RE: iommu=0 leading to panic when system defaults
	to using x2apic
Date: Mon, 13 Dec 2010 08:15:21 +0000
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To: Allen M Kay <allen.m.kay@intel.com>, Yang Z Zhang <yang.z.zhang@intel.com>, Keir Fraser <keir@xen.org>
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>>> On 11.12.10 at 01:07, "Kay, Allen M" <allen.m.kay@intel.com> wrote:
> Yes, interrupt remapping is needed to be the intermediary between =
legacy=20
> IOxAPIC and MSI devices and the new x2APIC in the CPU.=20

But isn't this only when there are APIC IDs beyond 255?

Jan

> -----Original Message-----
> From: Keir Fraser [mailto:keir.xen@gmail.com] On Behalf Of Keir Fraser
> Sent: Friday, December 10, 2010 10:50 AM
> To: Kay, Allen M; Jan Beulich; Zhang, Yang Z
> Cc: xen-devel@lists.xensource.com; Han, Weidong
> Subject: Re: [Xen-devel] iommu=3D0 leading to panic when system defaults =
to=20
> using x2apic
>=20
> Ah, and the interrupt remapping dependency is because PCI(e) devices =
cannot
> address 32-bit APIC IDs?
>=20
>  -- Keir
>=20
> On 10/12/2010 18:26, "Kay, Allen M" <allen.m.kay@intel.com> wrote:
>=20
>> The architectural requirement is actually between interrupt remapping =
and
>> x2apic.  Since interrupt remapping is part of the VT-d feature so =
current
>> software requires all VT-d features enabled in order for x2apic to =
be=20
> enabled.
>>=20
>> Strictly speaking DMA remapping is not required for x2apic.  However, =
queued
>> invalidation is required since interrupt remapping requires queued
>> invalidation.  So x2apic dependency is as follows:
>>=20
>>     x2apic->interrupt remapping->queued invalidation
>>=20
>> Due to historical reasons, the new VT-d features were built on top of =
the old
>> ones as they become available.  Is there a requirement to separate this =
out?
>> If so, we will need to re-design iommu boot parameter which took a =
while to
>> get it right so most systems can now boot successfully.
>>=20
>> Allen