From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Jan Beulich" Subject: [PATCH 5/5] x86: adjust other interrupt related section placement Date: Wed, 15 Dec 2010 11:21:47 +0000 Message-ID: <4D08B2DB02000078000281A9@vpn.id2.novell.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="=__Part527E1ADB.1__=" Return-path: List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: "xen-devel@lists.xensource.com" Cc: Yinghai Lu List-Id: xen-devel@lists.xenproject.org This is a MIME message. If you are reading this text, you may want to consider changing to a mail reader or gateway that understands how to properly handle MIME multipart messages. --=__Part527E1ADB.1__= Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Content-Disposition: inline ... and remove some variables the value of which is never used altogether. Signed-off-by: Jan Beulich --- a/xen/arch/ia64/xen/irq.c +++ b/xen/arch/ia64/xen/irq.c @@ -128,8 +128,6 @@ hw_irq_controller no_irq_type =3D { end_none }; =20 -atomic_t irq_err_count; - /* * Generic enable/disable code: this just calls * down into the PIC-specific version for the actual --- a/xen/arch/x86/apic.c +++ b/xen/arch/x86/apic.c @@ -165,7 +165,7 @@ void __init apic_intr_init(void) } =20 /* Using APIC to generate smp_local_timer_interrupt? */ -int using_apic_timer =3D 0; +static bool_t __read_mostly using_apic_timer; =20 static int enabled_via_apicbase; =20 @@ -1088,9 +1088,7 @@ __next: *************************************************************************= ****/ =20 /* used for system time scaling */ -static unsigned long bus_freq; /* KAF: pointer-size avoids compile = warns. */ -static u32 bus_cycle; /* length of one bus cycle in pico-secon= ds */ -static u32 bus_scale; /* scaling factor convert ns to bus = cycles */ +static u32 __read_mostly bus_scale; /* scaling factor convert ns to bus = cycles */ =20 /* * The timer chip is already set up at HZ interrupts per second here, @@ -1202,6 +1200,8 @@ static int __init calibrate_APIC_clock(v long tt1, tt2; long result; int i; + unsigned long bus_freq; /* KAF: pointer-size avoids compile warns. */ + u32 bus_cycle; /* length of one bus cycle in pico-seconds */ const int LOOPS =3D HZ/10; =20 apic_printk(APIC_VERBOSE, "calibrating APIC timer ...\n"); @@ -1416,7 +1416,6 @@ fastcall void smp_error_interrupt(struct apic_write(APIC_ESR, 0); v1 =3D apic_read(APIC_ESR); ack_APIC_irq(); - atomic_inc(&irq_err_count); =20 /* Here is what the APIC error bits mean: 0: Send CS error --- a/xen/arch/x86/i8259.c +++ b/xen/arch/x86/i8259.c @@ -284,7 +284,6 @@ static void mask_and_ack_8259A_irq(unsig printk("spurious 8259A interrupt: IRQ%d.\n", irq); spurious_irq_mask |=3D irqmask; } - atomic_inc(&irq_err_count); /* * Theoretically we do not have to handle this IRQ, * but in Linux this does not cause problems and is --- a/xen/arch/x86/io_apic.c +++ b/xen/arch/x86/io_apic.c @@ -38,8 +38,6 @@ #include #include =20 -atomic_t irq_mis_count; - /* Where if anywhere is the i8259 connect in external int mode */ static struct { int pin, apic; } ioapic_i8259 =3D { -1, -1 }; =20 @@ -61,8 +59,6 @@ int sis_apic_bug =3D -1; int __read_mostly nr_ioapic_registers[MAX_IO_APICS]; int __read_mostly nr_ioapics; =20 -int disable_timer_pin_1 __initdata; - /* * Rough estimation of how many shared IRQs there are, can * be changed anytime. @@ -1641,7 +1637,6 @@ static void mask_and_ack_level_ioapic_ir move_masked_irq(irq); =20 if ( !(v & (1 << (i & 0x1f))) ) { - atomic_inc(&irq_mis_count); spin_lock(&ioapic_lock); __edge_IO_APIC_irq(irq); __level_IO_APIC_irq(irq); @@ -1707,7 +1702,6 @@ static void end_level_ioapic_irq (unsign move_native_irq(irq); =20 if (!(v & (1 << (i & 0x1f)))) { - atomic_inc(&irq_mis_count); spin_lock(&ioapic_lock); __mask_IO_APIC_irq(irq); __edge_IO_APIC_irq(irq); @@ -1845,7 +1839,7 @@ static hw_irq_controller lapic_irq_type=20 * cycles as some i82489DX-based boards have glue logic that keeps the * 8259A interrupt line asserted until INTA. --macro */ -static inline void unlock_ExtINT_logic(void) +static void __init unlock_ExtINT_logic(void) { int apic, pin, i; struct IO_APIC_route_entry entry0, entry1; @@ -1902,15 +1896,13 @@ static inline void unlock_ExtINT_logic(v spin_unlock_irqrestore(&ioapic_lock, flags); } =20 -int timer_uses_ioapic_pin_0; - /* * This code may look a bit paranoid, but it's supposed to cooperate with * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ * is so screwy. Thanks to Brian Perkins for testing/hacking this beast * fanatically on his truly buggy board. */ -static inline void check_timer(void) +static void __init check_timer(void) { int apic1, pin1, apic2, pin2; int vector, ret; @@ -1949,9 +1941,6 @@ static inline void check_timer(void) pin2 =3D ioapic_i8259.pin; apic2 =3D ioapic_i8259.apic; =20 - if (pin1 =3D=3D 0) - timer_uses_ioapic_pin_0 =3D 1; - printk(KERN_INFO "..TIMER: vector=3D0x%02X apic1=3D%d pin1=3D%d = apic2=3D%d pin2=3D%d\n", vector, apic1, pin1, apic2, pin2); =20 @@ -1962,8 +1951,6 @@ static inline void check_timer(void) unmask_IO_APIC_irq(0); if (timer_irq_works()) { local_irq_restore(flags); - if (disable_timer_pin_1 > 0) - clear_IO_APIC_pin(apic1, pin1); return; } clear_IO_APIC_pin(apic1, pin1); @@ -2133,7 +2120,7 @@ void ioapic_resume(void) int __init io_apic_get_unique_id (int ioapic, int apic_id) { union IO_APIC_reg_00 reg_00; - static physid_mask_t apic_id_map =3D PHYSID_MASK_NONE; + static physid_mask_t __initdata apic_id_map =3D PHYSID_MASK_NONE; physid_mask_t tmp; unsigned long flags; int i =3D 0; --- a/xen/arch/x86/irq.c +++ b/xen/arch/x86/irq.c @@ -74,7 +74,7 @@ void unlock_vector_lock(void) spin_unlock(&vector_lock); } =20 -static int __bind_irq_vector(int irq, int vector, cpumask_t cpu_mask) +static int __init __bind_irq_vector(int irq, int vector, cpumask_t = cpu_mask) { cpumask_t online_mask; int cpu; @@ -100,7 +100,7 @@ static int __bind_irq_vector(int irq, in return 0; } =20 -int bind_irq_vector(int irq, int vector, cpumask_t cpu_mask) +int __init bind_irq_vector(int irq, int vector, cpumask_t cpu_mask) { unsigned long flags; int ret; @@ -328,8 +328,6 @@ hw_irq_controller no_irq_type =3D { end_none }; =20 -atomic_t irq_err_count; - int __assign_irq_vector(int irq, struct irq_cfg *cfg, const cpumask_t = *mask) { /* --- a/xen/include/asm-x86/io_apic.h +++ b/xen/include/asm-x86/io_apic.h @@ -190,7 +190,6 @@ extern int io_apic_get_unique_id (int io extern int io_apic_get_version (int ioapic); extern int io_apic_get_redir_entries (int ioapic); extern int io_apic_set_pci_routing (int ioapic, int pin, int irq, int = edge_level, int active_high_low); -extern int timer_uses_ioapic_pin_0; #endif /*CONFIG_ACPI_BOOT*/ =20 extern void init_ioapic_mappings(void); --- a/xen/include/asm-x86/irq.h +++ b/xen/include/asm-x86/irq.h @@ -102,9 +102,6 @@ void setup_ioapic_dest(void); =20 extern unsigned long io_apic_irqs; =20 -extern atomic_t irq_err_count; -extern atomic_t irq_mis_count; - DECLARE_PER_CPU(unsigned int, irq_count); =20 int pirq_shared(struct domain *d , int irq); --- a/xen/include/asm-x86/mpspec.h +++ b/xen/include/asm-x86/mpspec.h @@ -21,7 +21,6 @@ extern struct mpc_config_intsrc mp_irqs=20 extern int mpc_default_type; extern unsigned long mp_lapic_addr; extern int pic_mode; -extern int using_apic_timer; =20 #ifdef CONFIG_ACPI extern int mp_register_lapic (u32 id, u8 enabled); --=__Part527E1ADB.1__= Content-Type: text/plain; name="x86-irq-sections.patch" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="x86-irq-sections.patch" ... and remove some variables the value of which is never used=0Aaltogether= .=0A=0ASigned-off-by: Jan Beulich =0A=0A--- a/xen/arch= /ia64/xen/irq.c=0A+++ b/xen/arch/ia64/xen/irq.c=0A@@ -128,8 +128,6 @@ = hw_irq_controller no_irq_type =3D {=0A end_none=0A };=0A =0A-atomic_t = irq_err_count;=0A-=0A /*=0A * Generic enable/disable code: this just = calls=0A * down into the PIC-specific version for the actual=0A--- = a/xen/arch/x86/apic.c=0A+++ b/xen/arch/x86/apic.c=0A@@ -165,7 +165,7 @@ = void __init apic_intr_init(void)=0A }=0A =0A /* Using APIC to generate = smp_local_timer_interrupt? */=0A-int using_apic_timer =3D 0;=0A+static = bool_t __read_mostly using_apic_timer;=0A =0A static int enabled_via_apicba= se;=0A =0A@@ -1088,9 +1088,7 @@ __next:=0A *******************************= **********************************************/=0A =0A /* used for system = time scaling */=0A-static unsigned long bus_freq; /* KAF: pointer-size = avoids compile warns. */=0A-static u32 bus_cycle; /* length of = one bus cycle in pico-seconds */=0A-static u32 bus_scale; /* = scaling factor convert ns to bus cycles */=0A+static u32 __read_mostly = bus_scale; /* scaling factor convert ns to bus cycles */=0A =0A /*=0A * = The timer chip is already set up at HZ interrupts per second here,=0A@@ = -1202,6 +1200,8 @@ static int __init calibrate_APIC_clock(v=0A long = tt1, tt2;=0A long result;=0A int i;=0A+ unsigned long bus_freq; = /* KAF: pointer-size avoids compile warns. */=0A+ u32 bus_cycle; = /* length of one bus cycle in pico-seconds */=0A const int LOOPS =3D = HZ/10;=0A =0A apic_printk(APIC_VERBOSE, "calibrating APIC timer = ...\n");=0A@@ -1416,7 +1416,6 @@ fastcall void smp_error_interrupt(struct= =0A apic_write(APIC_ESR, 0);=0A v1 =3D apic_read(APIC_ESR);=0A = ack_APIC_irq();=0A- atomic_inc(&irq_err_count);=0A =0A /* Here is = what the APIC error bits mean:=0A 0: Send CS error=0A--- a/xen/arch/= x86/i8259.c=0A+++ b/xen/arch/x86/i8259.c=0A@@ -284,7 +284,6 @@ static void = mask_and_ack_8259A_irq(unsig=0A printk("spurious 8259A = interrupt: IRQ%d.\n", irq);=0A spurious_irq_mask |=3D = irqmask;=0A }=0A- atomic_inc(&irq_err_count);=0A = /*=0A * Theoretically we do not have to handle this IRQ,=0A = * but in Linux this does not cause problems and is=0A--- a/xen/arch/x86/= io_apic.c=0A+++ b/xen/arch/x86/io_apic.c=0A@@ -38,8 +38,6 @@=0A #include = =0A #include =0A =0A-atomic_t irq_mis_count;= =0A-=0A /* Where if anywhere is the i8259 connect in external int mode = */=0A static struct { int pin, apic; } ioapic_i8259 =3D { -1, -1 };=0A = =0A@@ -61,8 +59,6 @@ int sis_apic_bug =3D -1;=0A int __read_mostly = nr_ioapic_registers[MAX_IO_APICS];=0A int __read_mostly nr_ioapics;=0A = =0A-int disable_timer_pin_1 __initdata;=0A-=0A /*=0A * Rough estimation = of how many shared IRQs there are, can=0A * be changed anytime.=0A@@ = -1641,7 +1637,6 @@ static void mask_and_ack_level_ioapic_ir=0A = move_masked_irq(irq);=0A =0A if ( !(v & (1 << (i & 0x1f))) ) {=0A- = atomic_inc(&irq_mis_count);=0A spin_lock(&ioapic_lock);=0A = __edge_IO_APIC_irq(irq);=0A __level_IO_APIC_irq(irq);=0A@@ = -1707,7 +1702,6 @@ static void end_level_ioapic_irq (unsign=0A = move_native_irq(irq);=0A =0A if (!(v & (1 << (i & 0x1f)))) {=0A- = atomic_inc(&irq_mis_count);=0A spin_lock(&ioapic_lock);=0A = __mask_IO_APIC_irq(irq);=0A __edge_IO_APIC_irq(irq);=0A@@ -1845,7 = +1839,7 @@ static hw_irq_controller lapic_irq_type =0A * cycles as some = i82489DX-based boards have glue logic that keeps the=0A * 8259A interrupt = line asserted until INTA. --macro=0A */=0A-static inline void unlock_ExtI= NT_logic(void)=0A+static void __init unlock_ExtINT_logic(void)=0A {=0A = int apic, pin, i;=0A struct IO_APIC_route_entry entry0, entry1;=0A@@ = -1902,15 +1896,13 @@ static inline void unlock_ExtINT_logic(v=0A = spin_unlock_irqrestore(&ioapic_lock, flags);=0A }=0A =0A-int timer_uses_ioa= pic_pin_0;=0A-=0A /*=0A * This code may look a bit paranoid, but it's = supposed to cooperate with=0A * a wide range of boards and BIOS bugs. = Fortunately only the timer IRQ=0A * is so screwy. Thanks to Brian = Perkins for testing/hacking this beast=0A * fanatically on his truly = buggy board.=0A */=0A-static inline void check_timer(void)=0A+static void = __init check_timer(void)=0A {=0A int apic1, pin1, apic2, pin2;=0A = int vector, ret;=0A@@ -1949,9 +1941,6 @@ static inline void check_timer(voi= d)=0A pin2 =3D ioapic_i8259.pin;=0A apic2 =3D ioapic_i8259.apic;= =0A =0A- if (pin1 =3D=3D 0)=0A- timer_uses_ioapic_pin_0 =3D = 1;=0A-=0A printk(KERN_INFO "..TIMER: vector=3D0x%02X apic1=3D%d = pin1=3D%d apic2=3D%d pin2=3D%d\n",=0A vector, apic1, pin1, = apic2, pin2);=0A =0A@@ -1962,8 +1951,6 @@ static inline void check_timer(vo= id)=0A unmask_IO_APIC_irq(0);=0A if (timer_irq_works()) = {=0A local_irq_restore(flags);=0A- if (disable_timer= _pin_1 > 0)=0A- clear_IO_APIC_pin(apic1, pin1);=0A = return;=0A }=0A clear_IO_APIC_pin(apic1, pin1);=0A@@ = -2133,7 +2120,7 @@ void ioapic_resume(void)=0A int __init io_apic_get_uniqu= e_id (int ioapic, int apic_id)=0A {=0A union IO_APIC_reg_00 reg_00;=0A-= static physid_mask_t apic_id_map =3D PHYSID_MASK_NONE;=0A+ static = physid_mask_t __initdata apic_id_map =3D PHYSID_MASK_NONE;=0A = physid_mask_t tmp;=0A unsigned long flags;=0A int i =3D 0;=0A--- = a/xen/arch/x86/irq.c=0A+++ b/xen/arch/x86/irq.c=0A@@ -74,7 +74,7 @@ void = unlock_vector_lock(void)=0A spin_unlock(&vector_lock);=0A }=0A = =0A-static int __bind_irq_vector(int irq, int vector, cpumask_t = cpu_mask)=0A+static int __init __bind_irq_vector(int irq, int vector, = cpumask_t cpu_mask)=0A {=0A cpumask_t online_mask;=0A int = cpu;=0A@@ -100,7 +100,7 @@ static int __bind_irq_vector(int irq, in=0A = return 0;=0A }=0A =0A-int bind_irq_vector(int irq, int vector, cpumask_t = cpu_mask)=0A+int __init bind_irq_vector(int irq, int vector, cpumask_t = cpu_mask)=0A {=0A unsigned long flags;=0A int ret;=0A@@ -328,8 = +328,6 @@ hw_irq_controller no_irq_type =3D {=0A end_none=0A };=0A = =0A-atomic_t irq_err_count;=0A-=0A int __assign_irq_vector(int irq, struct = irq_cfg *cfg, const cpumask_t *mask)=0A {=0A /*=0A--- a/xen/include/asm= -x86/io_apic.h=0A+++ b/xen/include/asm-x86/io_apic.h=0A@@ -190,7 +190,6 @@ = extern int io_apic_get_unique_id (int io=0A extern int io_apic_get_version = (int ioapic);=0A extern int io_apic_get_redir_entries (int ioapic);=0A = extern int io_apic_set_pci_routing (int ioapic, int pin, int irq, int = edge_level, int active_high_low);=0A-extern int timer_uses_ioapic_pin_0;=0A= #endif /*CONFIG_ACPI_BOOT*/=0A =0A extern void init_ioapic_mappings(void);= =0A--- a/xen/include/asm-x86/irq.h=0A+++ b/xen/include/asm-x86/irq.h=0A@@ = -102,9 +102,6 @@ void setup_ioapic_dest(void);=0A =0A extern unsigned long = io_apic_irqs;=0A =0A-extern atomic_t irq_err_count;=0A-extern atomic_t = irq_mis_count;=0A-=0A DECLARE_PER_CPU(unsigned int, irq_count);=0A =0A int = pirq_shared(struct domain *d , int irq);=0A--- a/xen/include/asm-x86/mpspec= .h=0A+++ b/xen/include/asm-x86/mpspec.h=0A@@ -21,7 +21,6 @@ extern struct = mpc_config_intsrc mp_irqs =0A extern int mpc_default_type;=0A extern = unsigned long mp_lapic_addr;=0A extern int pic_mode;=0A-extern int = using_apic_timer;=0A =0A #ifdef CONFIG_ACPI=0A extern int mp_register_lapic= (u32 id, u8 enabled);=0A --=__Part527E1ADB.1__= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel --=__Part527E1ADB.1__=--