Re: [PATCH] Allow dom0 to write MSR IA32_ENERGY_PERF_BIAS

["Jan Beulich" <JBeulich@novell.com>]

>>> On 04.01.11 at 04:04, "Wei, Gang" <gang.wei@intel.com> wrote:
> Allow dom0 to write MSR IA32_ENERGY_PERF_BIAS
> 
> There is a new hardware feature, which lets system software to set Energy 
> Performance Preference. This is a opaque knob in the form of 
> IA32_ENERGY_PERF_BIAS MSR, which has a 4 bit Energy Performance Preference 
> Hint.
> 
> The support for this feature is indicated by CPUID.06H.ECX.bit3. Refer to 
> Intel Architectures Software Developer's Manual for more info.
> 
> Let dom0 tools to control it.
> 
> Signed-off-by: Wei Gang <gang.wei@intel.com>
> 
> diff -r 4e108cf56d07 xen/arch/x86/traps.c
> --- a/xen/arch/x86/traps.c	Mon Dec 27 08:00:09 2010 +0000
> +++ b/xen/arch/x86/traps.c	Sat Jan 01 20:01:43 2011 +0800
> @@ -2333,6 +2333,7 @@ static int emulate_privileged_op(struct 
>                  goto fail;
>              break;
>          case MSR_IA32_THERM_CONTROL:
> +        case MSR_IA32_ENERGY_PERF_BIAS:
>              if ( boot_cpu_data.x86_vendor != X86_VENDOR_INTEL )
>                  goto fail;
>              if ( (v->domain->domain_id != 0) || !v->domain->is_pinned )

Why would you allow this only if Dom0 has its vcpus pinned?

Jan