From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Jan Beulich" Subject: Re: [PATCH] Allow dom0 to write MSR IA32_ENERGY_PERF_BIAS Date: Tue, 04 Jan 2011 09:58:44 +0000 Message-ID: <4D22FD64020000780002A29B@vpn.id2.novell.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: Content-Disposition: inline List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: Gang Wei Cc: "xen-devel@lists.xensource.com" , Keir Fraser List-Id: xen-devel@lists.xenproject.org >>> On 04.01.11 at 04:04, "Wei, Gang" wrote: > Allow dom0 to write MSR IA32_ENERGY_PERF_BIAS >=20 > There is a new hardware feature, which lets system software to set = Energy=20 > Performance Preference. This is a opaque knob in the form of=20 > IA32_ENERGY_PERF_BIAS MSR, which has a 4 bit Energy Performance = Preference=20 > Hint. >=20 > The support for this feature is indicated by CPUID.06H.ECX.bit3. Refer = to=20 > Intel Architectures Software Developer's Manual for more info. >=20 > Let dom0 tools to control it. >=20 > Signed-off-by: Wei Gang >=20 > diff -r 4e108cf56d07 xen/arch/x86/traps.c > --- a/xen/arch/x86/traps.c Mon Dec 27 08:00:09 2010 +0000 > +++ b/xen/arch/x86/traps.c Sat Jan 01 20:01:43 2011 +0800 > @@ -2333,6 +2333,7 @@ static int emulate_privileged_op(struct=20 > goto fail; > break; > case MSR_IA32_THERM_CONTROL: > + case MSR_IA32_ENERGY_PERF_BIAS: > if ( boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL ) > goto fail; > if ( (v->domain->domain_id !=3D 0) || !v->domain->is_pinned = ) Why would you allow this only if Dom0 has its vcpus pinned? Jan