From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Jan Beulich" Subject: [PATCH] relax vCPU pinned checks Date: Wed, 05 Jan 2011 09:01:32 +0000 Message-ID: <4D24417C020000780002A68B@vpn.id2.novell.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="=__Part4E622A7C.0__=" Return-path: List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: "xen-devel@lists.xensource.com" List-Id: xen-devel@lists.xenproject.org This is a MIME message. If you are reading this text, you may want to consider changing to a mail reader or gateway that understands how to properly handle MIME multipart messages. --=__Part4E622A7C.0__= Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Content-Disposition: inline Both writing of certain MSRs and VCPUOP_get_physid make sense also for dynamically (perhaps temporarily) pinned vcpus. Likely a couple of other MSR writes (MSR_K8_HWCR, MSR_AMD64_NB_CFG, MSR_FAM10H_MMIO_CONF_BASE) would make sense to be restricted by an is_pinned() check too, possibly also some MSR reads. Signed-off-by: Jan Beulich --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -1036,7 +1036,7 @@ arch_do_vcpu_op( struct vcpu_get_physid cpu_id; =20 rc =3D -EINVAL; - if ( !v->domain->is_pinned ) + if ( !is_pinned(v) ) break; =20 cpu_id.phys_id =3D --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -2335,7 +2335,7 @@ static int emulate_privileged_op(struct=20 case MSR_IA32_THERM_CONTROL: if ( boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL ) goto fail; - if ( (v->domain->domain_id !=3D 0) || !v->domain->is_pinned ) + if ( (v->domain->domain_id !=3D 0) || !is_pinned(v) ) break; if ( wrmsr_safe(regs->ecx, msr_content) !=3D 0 ) goto fail; --- a/xen/include/xen/sched.h +++ b/xen/include/xen/sched.h @@ -634,6 +634,8 @@ void watchdog_domain_destroy(struct doma =20 #define is_hvm_domain(d) ((d)->is_hvm) #define is_hvm_vcpu(v) (is_hvm_domain(v->domain)) +#define is_pinned(v) ((v)->domain->is_pinned || \ + cpus_weight((v)->cpu_affinity) =3D=3D 1) #define need_iommu(d) ((d)->need_iommu) =20 void set_vcpu_migration_delay(unsigned int delay); --=__Part4E622A7C.0__= Content-Type: text/plain; name="relax-pinned-checks.patch" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="relax-pinned-checks.patch" Both writing of certain MSRs and VCPUOP_get_physid make sense also = for=0Adynamically (perhaps temporarily) pinned vcpus.=0A=0ALikely a couple = of other MSR writes (MSR_K8_HWCR, MSR_AMD64_NB_CFG,=0AMSR_FAM10H_MMIO_CONF_= BASE) would make sense to be restricted by an=0Ais_pinned() check too, = possibly also some MSR reads.=0A=0ASigned-off-by: Jan Beulich =0A=0A--- a/xen/arch/x86/domain.c=0A+++ b/xen/arch/x86/domain.c=0A@= @ -1036,7 +1036,7 @@ arch_do_vcpu_op(=0A struct vcpu_get_physid = cpu_id;=0A =0A rc =3D -EINVAL;=0A- if ( !v->domain->is_pinne= d )=0A+ if ( !is_pinned(v) )=0A break;=0A =0A = cpu_id.phys_id =3D=0A--- a/xen/arch/x86/traps.c=0A+++ b/xen/arch/x86/traps.= c=0A@@ -2335,7 +2335,7 @@ static int emulate_privileged_op(struct =0A = case MSR_IA32_THERM_CONTROL:=0A if ( boot_cpu_data.x86_vendo= r !=3D X86_VENDOR_INTEL )=0A goto fail;=0A- if = ( (v->domain->domain_id !=3D 0) || !v->domain->is_pinned )=0A+ = if ( (v->domain->domain_id !=3D 0) || !is_pinned(v) )=0A = break;=0A if ( wrmsr_safe(regs->ecx, msr_content) !=3D 0 )=0A = goto fail;=0A--- a/xen/include/xen/sched.h=0A+++ b/xen/inclu= de/xen/sched.h=0A@@ -634,6 +634,8 @@ void watchdog_domain_destroy(struct = doma=0A =0A #define is_hvm_domain(d) ((d)->is_hvm)=0A #define is_hvm_vcpu(v= ) (is_hvm_domain(v->domain))=0A+#define is_pinned(v) ((v)->domain->is= _pinned || \=0A+ cpus_weight((v)->cpu_affinity) = =3D=3D 1)=0A #define need_iommu(d) ((d)->need_iommu)=0A =0A void = set_vcpu_migration_delay(unsigned int delay);=0A --=__Part4E622A7C.0__= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel --=__Part4E622A7C.0__=--