[PATCH] MTRR: clear DramModEn bit of sys_cfg MSR

[Wei Huang <wei.huang2@amd.com>]

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Some buggy BIOS might set sys_cfg DramModEn bit to 1, which can cause 
unexpected behavior on AMD platforms. This patch clears DramModEn bit. 
The patch was derived from upstream kernel patch (see 
https://patchwork.kernel.org/patch/11425/).

Signed-off-by: Wei Huang <wei.huang2@amd.com>





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# HG changeset patch
# User Wei Huang <wei.huang2@amd.com>
# Date 1301955822 18000
# Node ID e9ab70bf676a89e5c2f3380622c335ee8f55ede3
# Parent  5a10b635262c0d5816415f616ade21264fc53f64
MTRR: clear AMD SYS_CFG DramModEn to 0

Some buggy BIOS might set SYS_CFG DramModEn bit to 1, which can cause unexpected behavior on AMD platforms. This patch clears DramModEn bit if it is 1. The patch was derived from upstream kernel patch (see https://patchwork.kernel.org/patch/11425/).

Signed-off-by: Wei Huang <wei.huang2@amd.com>

diff -r 5a10b635262c -r e9ab70bf676a xen/arch/x86/cpu/mtrr/generic.c
--- a/xen/arch/x86/cpu/mtrr/generic.c	Mon Apr 04 13:29:38 2011 -0500
+++ b/xen/arch/x86/cpu/mtrr/generic.c	Mon Apr 04 17:23:42 2011 -0500
@@ -34,11 +34,36 @@
 	rdmsrl(MTRRphysMask_MSR(index), vr->mask);
 }
 
+/*
+ * BIOS is expected to clear MtrrFixDramModEn bit. According to AMD BKDG : 
+ * "The MtrrFixDramModEn bit should be set to 1 during BIOS initalization of 
+ * the fixed MTRRs, then cleared to 0 for operation."
+ */
+static inline void amd_check_syscfg_dram_mod_en(void)
+{
+    uint64_t syscfg;
+
+    if (!((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
+          (boot_cpu_data.x86 >= 0x0f)))
+        return;
+
+    rdmsrl(MSR_K8_SYSCFG, syscfg);
+    if (syscfg & K8_MTRRFIXRANGE_DRAM_MODIFY) {
+        printk(KERN_ERR "MTRR: CPU %u: SYSCFG[MtrrFixDramModEn]"
+               " not cleared by BIOS, clearing this bit\n",
+               smp_processor_id());
+        syscfg &= ~K8_MTRRFIXRANGE_DRAM_MODIFY;
+        mtrr_wrmsr(MSR_K8_SYSCFG, syscfg);
+    }
+}
+
 static void
 get_fixed_ranges(mtrr_type * frs)
 {
 	uint64_t *p = (uint64_t *) frs;
 	int i;
+
+        amd_check_syscfg_dram_mod_en();
 
 	rdmsrl(MTRRfix64K_00000_MSR, p[0]);
 
@@ -116,20 +141,6 @@
 }
 
 /**
- * Enable and allow read/write of extended fixed-range MTRR bits on K8 CPUs
- * see AMD publication no. 24593, chapter 3.2.1 for more information
- */
-static inline void k8_enable_fixed_iorrs(void)
-{
-	uint64_t msr_content;
-
-	rdmsrl(MSR_K8_SYSCFG, msr_content);
-	mtrr_wrmsr(MSR_K8_SYSCFG, msr_content 
-				| K8_MTRRFIXRANGE_DRAM_ENABLE
-				| K8_MTRRFIXRANGE_DRAM_MODIFY);
-}
-
-/**
  * Checks and updates an fixed-range MTRR if it differs from the value it
  * should have. If K8 extenstions are wanted, update the K8 SYSCFG MSR also.
  * see AMD publication no. 24593, chapter 7.8.1, page 233 for more information
@@ -145,10 +156,6 @@
 	val = ((uint64_t)msrwords[1] << 32) | msrwords[0];
 
 	if (msr_content != val) {
-		if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
-		    boot_cpu_data.x86 == 15 &&
-		    ((msrwords[0] | msrwords[1]) & K8_MTRR_RDMEM_WRMEM_MASK))
-			k8_enable_fixed_iorrs();
 		mtrr_wrmsr(msr, val);
 		*changed = TRUE;
 	}
@@ -211,6 +218,8 @@
 	unsigned long long *saved = (unsigned long long *) frs;
 	int changed = FALSE;
 	int block=-1, range;
+
+        amd_check_syscfg_dram_mod_en();
 
 	while (fixed_range_blocks[++block].ranges)
 	    for (range=0; range < fixed_range_blocks[block].ranges; range++)

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