From: "Jan Beulich" <JBeulich@novell.com>
To: Wei Wang2 <wei.wang2@amd.com>
Cc: Boris Ostrovsky <boris.ostrovsky@amd.com>,
Wei Huang2 <Wei.Huang2@amd.com>,
"xen-devel@lists.xensource.com" <xen-devel@lists.xensource.com>
Subject: Re: [PATCH] AMD IOMMU: Fix an interrupt remapping issue
Date: Fri, 08 Apr 2011 12:26:34 +0100 [thread overview]
Message-ID: <4D9F0D0A020000780003A931@vpn.id2.novell.com> (raw)
In-Reply-To: <201104081252.04840.wei.wang2@amd.com>
>>> On 08.04.11 at 12:52, Wei Wang2 <wei.wang2@amd.com> wrote:
> Some device could generate bogus interrupts if an IO-APIC RTE and an iommu
> interrupt remapping entry are not consistent during 2 adjacent 64bits IO-APIC
>
> RTE updates. For example, if the 2nd operation updates destination bits in
> RTE for SATA device and unmask it, in some case, SATA device will assert
> ioapic pin to generate interrupt immediately using new destination but iommu
>
> could still translate it into the old destination, then dom0 would be
> confused. To fix that, we sync up interrupt remapping entry with IO-APIC IRE
> on every 32 bits operation and foward IOAPIC RTE updates after interrupt
> remapping table has been changed.
>
> Jan, This patch fixes SATA device issue we observed (Bug #680824), please
> review it. Thanks!
Sure - once you attach the actual patch ;-)
Jan
next prev parent reply other threads:[~2011-04-08 11:26 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-04-08 10:52 [PATCH] AMD IOMMU: Fix an interrupt remapping issue Wei Wang2
2011-04-08 11:26 ` Jan Beulich [this message]
-- strict thread matches above, loose matches on Subject: below --
2011-04-08 11:35 Wei Wang2
2011-04-08 13:43 ` Jan Beulich
2011-04-08 14:26 ` Wei Wang2
2011-04-08 14:39 ` Jan Beulich
2011-04-08 15:06 ` Wei Wang2
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