From: "Jan Beulich" <JBeulich@novell.com>
To: Winston L Wang <winston.l.wang@intel.com>
Cc: Jinsong Liu <jinsong.liu@intel.com>,
"xen-devel@lists.xensource.com" <xen-devel@lists.xensource.com>,
KeirFraser <keir@xen.org>,
Yunhong Jiang <yunhong.jiang@intel.com>,
Donald D Dugger <donald.d.dugger@intel.com>,
Xin Li <xin.li@intel.com>
Subject: Re: Re: system freeze when processor.ko is loaded
Date: Tue, 12 Apr 2011 08:03:01 +0100 [thread overview]
Message-ID: <4DA41545020000780003B00F@vpn.id2.novell.com> (raw)
In-Reply-To: <54B2EB610B7F1340BB6A0D4CA04A4F1001008E2FED@orsmsx505.amr.corp.intel.com>
>>> On 12.04.11 at 00:35, "Wang, Winston L" <winston.l.wang@intel.com> wrote:
> I think restore only the lower 32bit TSC is good enough, why do we need to
> touch upper 32 bit TSC?
You just can't: A wrmsr to this MSR always updates the full 64-bits,
just that on some CPUs this update implies the upper 32 bits getting
zeroed.
And even if you could, it wouldn't be easy to deal with the situation
where the update would carry into the upper 32 bits.
Jan
> 1. I would not think if any processor's deep c-state wakeup from idle can
> more than 100 ms.
> 2. For 3GHZ processor lower 32bit TSC wrapper around time is ~2.83 Sec.
> 3. The platform timer (22bit ACPI timer) wrapper around is 2.34 sec (this is
> used for counting the delta before enter deep_cstate and before wakeup)
> Just need to change cstate_restore_tsc() and only patch back the delta time
> to the lower 32 bit TSC to make that simple?
>
> Winston,
next prev parent reply other threads:[~2011-04-12 7:03 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <d6cfc1ce-e4b3-47dc-ae83-8d0c341988b3@rrsmsx606.amr.corp.intel.com>
2011-04-11 22:35 ` Re: system freeze when processor.ko is loaded Wang, Winston L
2011-04-12 7:03 ` Jan Beulich [this message]
2011-04-12 17:27 ` Wang, Winston L
2011-04-12 17:32 ` Keir Fraser
2011-04-13 6:50 ` Jan Beulich
2011-04-13 18:06 ` Wang, Winston L
2011-04-17 19:38 ` Martin Wilck
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