From: Wei Huang <wei.huang2@amd.com>
To: "'xen-devel@lists.xensource.com'" <xen-devel@lists.xensource.com>
Subject: [PATCH][RFC] FPU LWP 0/5: patch description
Date: Thu, 14 Apr 2011 15:37:27 -0500 [thread overview]
Message-ID: <4DA75B07.6010503@amd.com> (raw)
The following patches support AMD lightweight profiling.
Because LWP isn't tracked by CR0.TS bit, we clean up the FPU code to
handle lazy and unlazy FPU states differently. Lazy FPU state (such as
SSE, YMM) is handled when #NM is triggered. Unlazy state, such as LWP,
is saved and restored on each vcpu context switch. To simplify the code,
we also add a mask option to xsave/xrstor function.
Thanks,
-Wei
next reply other threads:[~2011-04-14 20:37 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-04-14 20:37 Wei Huang [this message]
2011-04-14 21:09 ` [PATCH][RFC] FPU LWP 0/5: patch description Keir Fraser
2011-04-14 22:57 ` Wei Huang
2011-04-15 20:16 ` Dan Magenheimer
2011-04-15 20:23 ` Huang2, Wei
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