From mboxrd@z Thu Jan  1 00:00:00 1970
From: Wei Huang <wei.huang2@amd.com>
Subject: [PATCH][RFC] FPU LWP 0/5: patch description
Date: Thu, 14 Apr 2011 15:37:27 -0500
Message-ID: <4DA75B07.6010503@amd.com>
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The following patches support AMD lightweight profiling.

Because LWP isn't tracked by CR0.TS bit, we clean up the FPU code to 
handle lazy and unlazy FPU states differently. Lazy FPU state (such as 
SSE, YMM) is handled when #NM is triggered. Unlazy state, such as LWP, 
is saved and restored on each vcpu context switch. To simplify the code, 
we also add a mask option to xsave/xrstor function.

Thanks,
-Wei