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* [PATCH][RFC] FPU LWP 0/5: patch description
@ 2011-04-14 20:37 Wei Huang
  2011-04-14 21:09 ` Keir Fraser
  0 siblings, 1 reply; 5+ messages in thread
From: Wei Huang @ 2011-04-14 20:37 UTC (permalink / raw)
  To: 'xen-devel@lists.xensource.com'

The following patches support AMD lightweight profiling.

Because LWP isn't tracked by CR0.TS bit, we clean up the FPU code to 
handle lazy and unlazy FPU states differently. Lazy FPU state (such as 
SSE, YMM) is handled when #NM is triggered. Unlazy state, such as LWP, 
is saved and restored on each vcpu context switch. To simplify the code, 
we also add a mask option to xsave/xrstor function.

Thanks,
-Wei

^ permalink raw reply	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2011-04-15 20:23 UTC | newest]

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-- links below jump to the message on this page --
2011-04-14 20:37 [PATCH][RFC] FPU LWP 0/5: patch description Wei Huang
2011-04-14 21:09 ` Keir Fraser
2011-04-14 22:57   ` Wei Huang
2011-04-15 20:16     ` Dan Magenheimer
2011-04-15 20:23       ` Huang2, Wei

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