From: Andre Przywara <andre.przywara@amd.com>
To: Keir Fraser <keir.fraser@eu.citrix.com>
Cc: xen-devel <xen-devel@lists.xensource.com>
Subject: [PATCH 0/5] svm: implement new DecodeAssist feature
Date: Fri, 15 Apr 2011 14:16:25 +0200 [thread overview]
Message-ID: <4DA83719.5080106@amd.com> (raw)
Hi,
newer AMD SVM implementations (starting with Bulldozer) have some
additions to SVM called DecodeAssist. These bits improve and simplify
the handling of some intercepts, now more information is provided in the
VMCB already and saves us from decoding this information "manually".
These new features are described in recent editions of the APM Vol.2
manual, chapter 15.33.
The first patch moves some code from VMX into HVM to be later used by
SVM. The second patch adds the newly defined bits to VMCB and CPUID.
Patch 3 to 5 implement three parts of the feature set, more details in
the specific emails.
Please comment.
All patches:
Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Regards,
Andre.
--
Andre Przywara
AMD-Operating System Research Center (OSRC), Dresden, Germany
next reply other threads:[~2011-04-15 12:16 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-04-15 12:16 Andre Przywara [this message]
2011-04-15 12:21 ` [PATCH 1/5] vmx/hvm: move mov-cr handling functions to generic HVM code Andre Przywara
2011-04-18 8:48 ` Keir Fraser
2011-04-15 12:21 ` [PATCH 2/5] svm: add bit definitions for SVM DecodeAssist Andre Przywara
2011-04-15 12:22 ` [PATCH 3/5] svm: implement instruction fetch part of DecodeAssist Andre Przywara
2011-04-18 9:10 ` Keir Fraser
2011-04-18 12:37 ` Keir Fraser
2011-04-15 12:23 ` [PATCH 4/5] svm: implement CR access " Andre Przywara
2011-04-15 12:24 ` [PATCH 5/5] svm: implement INVLPG " Andre Przywara
2011-04-18 9:07 ` Keir Fraser
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