From: "Jan Beulich" <JBeulich@novell.com>
To: Wei Huang <wei.huang2@amd.com>
Cc: "xen-devel@lists.xensource.com" <xen-devel@lists.xensource.com>,
Keir Fraser <keir@xen.org>
Subject: Re: [PATCH] FPU LWP 5/8: add a mask option to xsave() and xrstor()
Date: Wed, 04 May 2011 08:02:37 +0100 [thread overview]
Message-ID: <4DC1162D020000780003F9BA@vpn.id2.novell.com> (raw)
In-Reply-To: <4DC062D3.9000906@amd.com>
>>> On 03.05.11 at 22:17, Wei Huang <wei.huang2@amd.com> wrote:
>+#define XSTATE_LAZY (XSTATE_FP | XSTATE_SSE | XSTATE_YMM)
>+#define XSTATE_NONLAZY (XSTATE_LWP)
>+#define XSTATE_ALL (~0)
As said before, this isn't forward compatible. New bits added in
future hardware should explicitly *not* require changes to the OS
(or hypervisor in our case). If you're certain LWP will remain the
only piece not controlled via CR0.TS, then you'll want
#define XSTATE_LAZY (XSTATE_ALL & ~XSTATE_NONLAZY)
If you aren't (and I'm afraid you can't), then you'll have to ask
your hardware guys to provide a means to detect which of the
bits cover state not controlled by CR0.TS, and set these masks
dynamically.
Jan
next prev parent reply other threads:[~2011-05-04 7:02 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-05-03 20:17 [PATCH] FPU LWP 5/8: add a mask option to xsave() and xrstor() Wei Huang
2011-05-04 7:02 ` Jan Beulich [this message]
2011-05-04 16:03 ` Wei Huang
2011-05-05 7:09 ` Jan Beulich
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