From mboxrd@z Thu Jan  1 00:00:00 1970
From: "Jan Beulich" <JBeulich@novell.com>
Subject: Re: [PATCH] FPU LWP 5/8: add a mask option to xsave()
	and xrstor()
Date: Wed, 04 May 2011 08:02:37 +0100
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To: Wei Huang <wei.huang2@amd.com>
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>>> On 03.05.11 at 22:17, Wei Huang <wei.huang2@amd.com> wrote:
>+#define XSTATE_LAZY    (XSTATE_FP | XSTATE_SSE | XSTATE_YMM)
>+#define XSTATE_NONLAZY (XSTATE_LWP)
>+#define XSTATE_ALL     (~0)

As said before, this isn't forward compatible. New bits added in
future hardware should explicitly *not* require changes to the OS
(or hypervisor in our case). If you're certain LWP will remain the
only piece not controlled via CR0.TS, then you'll want

#define XSTATE_LAZY    (XSTATE_ALL & ~XSTATE_NONLAZY)

If you aren't (and I'm afraid you can't), then you'll have to ask
your hardware guys to provide a means to detect which of the
bits cover state not controlled by CR0.TS, and set these masks
dynamically.

Jan