From: "Jan Beulich" <JBeulich@novell.com>
To: Wei Huang <wei.huang2@amd.com>
Cc: "xen-devel@lists.xensource.com" <xen-devel@lists.xensource.com>,
KeirFraser <keir@xen.org>
Subject: Re: [PATCH] FPU LWP 5/8: add a mask option to xsave() and xrstor()
Date: Thu, 05 May 2011 08:09:24 +0100 [thread overview]
Message-ID: <4DC26944020000780003FC33@vpn.id2.novell.com> (raw)
In-Reply-To: <4DC178CF.2070307@amd.com>
>>> On 04.05.11 at 18:03, Wei Huang <wei.huang2@amd.com> wrote:
> Hi Jan,
>
> That is a good point. So far there isn't a way to decide which bits are
> guarded by CR0.TS. I will bring it up to our design team. I guess LWP
> will the only exception for a long while. Is the first approach
> sufficient/acceptable to you for now?
>
> #define XSTATE_LAZY (XSTATE_ALL & ~XSTATE_NONLAZY)
Yes.
Jan
prev parent reply other threads:[~2011-05-05 7:09 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-05-03 20:17 [PATCH] FPU LWP 5/8: add a mask option to xsave() and xrstor() Wei Huang
2011-05-04 7:02 ` Jan Beulich
2011-05-04 16:03 ` Wei Huang
2011-05-05 7:09 ` Jan Beulich [this message]
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