From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Jan Beulich" Subject: Re: [PATCH 2/3] xenoprof: Add support for AMD Family 15h processors Date: Thu, 05 May 2011 08:38:18 +0100 Message-ID: <4DC2700A020000780003FC63@vpn.id2.novell.com> References: <4DC1F53B.4050201@amd.com> <4DC1F8B2.7080001@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: <4DC1F8B2.7080001@amd.com> Content-Disposition: inline List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: Jacob Shin Cc: xen-devel@lists.xensource.com List-Id: xen-devel@lists.xenproject.org >>> On 05.05.11 at 03:09, Jacob Shin wrote: > # HG changeset patch > # User Jacob Shin > # Date 1304524596 18000 > # Node ID 349a9e537940f8bc340a2055cb5068b58809042f > # Parent eeb1bb50ba13c36e44d4994e01d82d294f3c584a > xenoprof: Add support for AMD Family 15h processors >=20 > AMD Family 15h CPU mirrors legacy K7 performance monitor counters to > a new location, and adds 2 new counters. This patch updates xenoprof > to take advantage of the new counters. >=20 > Signed-off-by: Jacob Shin >=20 > diff -r eeb1bb50ba13 -r 349a9e537940 xen/arch/x86/oprofile/nmi_int.c > --- a/xen/arch/x86/oprofile/nmi_int.c Tue May 03 17:26:33 2011 -0500 > +++ b/xen/arch/x86/oprofile/nmi_int.c Wed May 04 10:56:36 2011 -0500 > @@ -30,7 +30,7 @@ struct op_counter_config counter_config[ > struct op_counter_config counter_config[OP_MAX_COUNTER]; > struct op_ibs_config ibs_config; > =20 > -static struct op_x86_model_spec const *__read_mostly model; > +struct op_x86_model_spec const *__read_mostly model; > static struct op_msrs cpu_msrs[NR_CPUS]; > static unsigned long saved_lvtpc[NR_CPUS]; > =20 > @@ -446,7 +446,7 @@ static int __init nmi_init(void) > cpu_type =3D "x86-64/family14h"; > break; > case 0x15: > - model =3D &op_athlon_spec; > + model =3D &op_fam15h_spec; Let's please call this op_amd_fam15h_spec. Jan > cpu_type =3D "x86-64/family15h"; > break; > } > diff -r eeb1bb50ba13 -r 349a9e537940 xen/arch/x86/oprofile/op_model_athlo= n.c > --- a/xen/arch/x86/oprofile/op_model_athlon.c Tue May 03 17:26:33 2011 = -0500 > +++ b/xen/arch/x86/oprofile/op_model_athlon.c Wed May 04 10:56:36 2011 = -0500 > @@ -24,8 +24,13 @@ > #include "op_x86_model.h" > #include "op_counter.h" > =20 > -#define NUM_COUNTERS 4 > -#define NUM_CONTROLS 4 > +#define K7_NUM_COUNTERS 4 > +#define K7_NUM_CONTROLS 4 > + > +#define FAM15H_NUM_COUNTERS 6 > +#define FAM15H_NUM_CONTROLS 6 > + > +#define MAX_COUNTERS FAM15H_NUM_COUNTERS > =20 > #define CTR_READ(msr_content,msrs,c) do {rdmsrl(msrs->counters[(c)].addr= ,=20 > (msr_content));} while (0) > #define CTR_WRITE(l,msrs,c) do {wrmsr(msrs->counters[(c)].addr, = -(unsigned=20 > int)(l), -1);} while (0) > @@ -44,9 +49,10 @@ > #define CTRL_SET_HOST_ONLY(val, h) (val |=3D ((h & 0x1ULL) << 41)) > #define CTRL_SET_GUEST_ONLY(val, h) (val |=3D ((h & 0x1ULL) << 40)) > =20 > -static unsigned long reset_value[NUM_COUNTERS]; > +static unsigned long reset_value[MAX_COUNTERS]; > =20 > extern char svm_stgi_label[]; > +extern struct op_x86_model_spec const *__read_mostly model; > =20 > #ifdef CONFIG_X86_64 > u32 ibs_caps =3D 0; > @@ -175,26 +181,44 @@ static void athlon_fill_in_addresses(str > msrs->controls[3].addr =3D MSR_K7_EVNTSEL3; > } > =20 > -=20 > +static void fam15h_fill_in_addresses(struct op_msrs * const msrs) > +{ > + msrs->counters[0].addr =3D MSR_FAM15H_PERFCTR0; > + msrs->counters[1].addr =3D MSR_FAM15H_PERFCTR1; > + msrs->counters[2].addr =3D MSR_FAM15H_PERFCTR2; > + msrs->counters[3].addr =3D MSR_FAM15H_PERFCTR3; > + msrs->counters[4].addr =3D MSR_FAM15H_PERFCTR4; > + msrs->counters[5].addr =3D MSR_FAM15H_PERFCTR5; > + > + msrs->controls[0].addr =3D MSR_FAM15H_EVNTSEL0; > + msrs->controls[1].addr =3D MSR_FAM15H_EVNTSEL1; > + msrs->controls[2].addr =3D MSR_FAM15H_EVNTSEL2; > + msrs->controls[3].addr =3D MSR_FAM15H_EVNTSEL3; > + msrs->controls[4].addr =3D MSR_FAM15H_EVNTSEL4; > + msrs->controls[5].addr =3D MSR_FAM15H_EVNTSEL5; > +} > + > static void athlon_setup_ctrs(struct op_msrs const * const msrs) > { > uint64_t msr_content; > int i; > + unsigned int const nr_ctrs =3D model->num_counters; > + unsigned int const nr_ctrls =3D model->num_controls; > =20 > /* clear all counters */ > - for (i =3D 0 ; i < NUM_CONTROLS; ++i) { > + for (i =3D 0 ; i < nr_ctrls; ++i) { > CTRL_READ(msr_content, msrs, i); > CTRL_CLEAR(msr_content); > CTRL_WRITE(msr_content, msrs, i); > } > =09 > /* avoid a false detection of ctr overflows in NMI handler */ > - for (i =3D 0; i < NUM_COUNTERS; ++i) { > + for (i =3D 0; i < nr_ctrs; ++i) { > CTR_WRITE(1, msrs, i); > } > =20 > /* enable active counters */ > - for (i =3D 0; i < NUM_COUNTERS; ++i) { > + for (i =3D 0; i < nr_ctrs; ++i) { > if (counter_config[i].enabled) { > reset_value[i] =3D counter_config[i].count; > =20 > @@ -300,6 +324,7 @@ static int athlon_check_ctrs(unsigned in > int mode =3D 0; > struct vcpu *v =3D current; > struct cpu_user_regs *guest_regs =3D guest_cpu_user_regs(); > + unsigned int const nr_ctrs =3D model->num_counters; > =20 > if (!guest_mode(regs) && > (regs->eip =3D=3D (unsigned long)svm_stgi_label)) { > @@ -312,7 +337,7 @@ static int athlon_check_ctrs(unsigned in > mode =3D xenoprofile_get_mode(v, regs); > } > =20 > - for (i =3D 0 ; i < NUM_COUNTERS; ++i) { > + for (i =3D 0 ; i < nr_ctrs; ++i) { > CTR_READ(msr_content, msrs, i); > if (CTR_OVERFLOWED(msr_content)) { > xenoprof_log_event(current, regs, eip, mode, i); > @@ -373,7 +398,8 @@ static void athlon_start(struct op_msrs=20 > { > uint64_t msr_content; > int i; > - for (i =3D 0 ; i < NUM_COUNTERS ; ++i) { > + unsigned int const nr_ctrs =3D model->num_counters; > + for (i =3D 0 ; i < nr_ctrs ; ++i) { > if (reset_value[i]) { > CTRL_READ(msr_content, msrs, i); > CTRL_SET_ACTIVE(msr_content); > @@ -401,10 +427,11 @@ static void athlon_stop(struct op_msrs c > { > uint64_t msr_content; > int i; > + unsigned int const nr_ctrs =3D model->num_counters; > =20 > /* Subtle: stop on all counters to avoid race with > * setting our pm callback */ > - for (i =3D 0 ; i < NUM_COUNTERS ; ++i) { > + for (i =3D 0 ; i < nr_ctrs ; ++i) { > CTRL_READ(msr_content, msrs, i); > CTRL_SET_INACTIVE(msr_content); > CTRL_WRITE(msr_content, msrs, i); > @@ -512,11 +539,21 @@ void __init ibs_init(void) > #endif /* CONFIG_X86_64 */ > =20 > struct op_x86_model_spec const op_athlon_spec =3D { > - .num_counters =3D NUM_COUNTERS, > - .num_controls =3D NUM_CONTROLS, > + .num_counters =3D K7_NUM_COUNTERS, > + .num_controls =3D K7_NUM_CONTROLS, > .fill_in_addresses =3D &athlon_fill_in_addresses, > .setup_ctrs =3D &athlon_setup_ctrs, > .check_ctrs =3D &athlon_check_ctrs, > .start =3D &athlon_start, > .stop =3D &athlon_stop > }; > + > +struct op_x86_model_spec const op_fam15h_spec =3D { > + .num_counters =3D FAM15H_NUM_COUNTERS, > + .num_controls =3D FAM15H_NUM_CONTROLS, > + .fill_in_addresses =3D &fam15h_fill_in_addresses, > + .setup_ctrs =3D &athlon_setup_ctrs, > + .check_ctrs =3D &athlon_check_ctrs, > + .start =3D &athlon_start, > + .stop =3D &athlon_stop > +}; > diff -r eeb1bb50ba13 -r 349a9e537940 xen/arch/x86/oprofile/op_x86_model.h= > --- a/xen/arch/x86/oprofile/op_x86_model.h Tue May 03 17:26:33 2011 = -0500 > +++ b/xen/arch/x86/oprofile/op_x86_model.h Wed May 04 10:56:36 2011 = -0500 > @@ -48,6 +48,7 @@ extern struct op_x86_model_spec const op > extern struct op_x86_model_spec const op_p4_spec; > extern struct op_x86_model_spec const op_p4_ht2_spec; > extern struct op_x86_model_spec const op_athlon_spec; > +extern struct op_x86_model_spec const op_fam15h_spec; > =20 > void arch_perfmon_setup_counters(void); > #endif /* OP_X86_MODEL_H */ > diff -r eeb1bb50ba13 -r 349a9e537940 xen/include/asm-x86/msr-index.h > --- a/xen/include/asm-x86/msr-index.h Tue May 03 17:26:33 2011 -0500 > +++ b/xen/include/asm-x86/msr-index.h Wed May 04 10:56:36 2011 -0500 > @@ -223,6 +223,19 @@ > #define MSR_K8_ENABLE_C1E 0xc0010055 > #define MSR_K8_VM_CR 0xc0010114 > #define MSR_K8_VM_HSAVE_PA 0xc0010117 > + > +#define MSR_FAM15H_EVNTSEL0 0xc0010200 > +#define MSR_FAM15H_PERFCTR0 0xc0010201 > +#define MSR_FAM15H_EVNTSEL1 0xc0010202 > +#define MSR_FAM15H_PERFCTR1 0xc0010203 > +#define MSR_FAM15H_EVNTSEL2 0xc0010204 > +#define MSR_FAM15H_PERFCTR2 0xc0010205 > +#define MSR_FAM15H_EVNTSEL3 0xc0010206 > +#define MSR_FAM15H_PERFCTR3 0xc0010207 > +#define MSR_FAM15H_EVNTSEL4 0xc0010208 > +#define MSR_FAM15H_PERFCTR4 0xc0010209 > +#define MSR_FAM15H_EVNTSEL5 0xc001020a > +#define MSR_FAM15H_PERFCTR5 0xc001020b > =20 > #define MSR_K8_FEATURE_MASK 0xc0011004 > #define MSR_K8_EXT_FEATURE_MASK 0xc0011005 >=20 >=20 > _______________________________________________ > Xen-devel mailing list > Xen-devel@lists.xensource.com=20 > http://lists.xensource.com/xen-devel=20