From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Jan Beulich" Subject: [PATCH] x86: add support for newest version of Intel CPUID masking Date: Fri, 13 May 2011 12:01:04 +0100 Message-ID: <4DCD2B900200007800041412@vpn.id2.novell.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="=__Part87AB0A60.1__=" Return-path: List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: "xen-devel@lists.xensource.com" Cc: Jun Nakajima List-Id: xen-devel@lists.xenproject.org This is a MIME message. If you are reading this text, you may want to consider changing to a mail reader or gateway that understands how to properly handle MIME multipart messages. --=__Part87AB0A60.1__= Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Content-Disposition: inline This follows appnote 485 rev 037, with a slight deviation in the leaf 0xd masking: The document states that ECX and EDX outputs get masked, but with the bit fields of interest being in EAX and EDX (while ECX holds other information that doesn't make sense to be masked), option and variable names use 'eax' instead. (Jun, would be nice if you could confirm this.) Signed-off-by: Jan Beulich --- 2011-04-29.orig/xen/arch/x86/cpu/common.c 2011-04-26 08:19:36.0000000= 00 +0200 +++ 2011-04-29/xen/arch/x86/cpu/common.c 2011-05-12 18:10:10.0000000= 00 +0200 @@ -20,10 +20,17 @@ size_param("cachesize", cachesize_overri =20 static bool_t __cpuinitdata use_xsave =3D 1; boolean_param("xsave", use_xsave); + unsigned int __devinitdata opt_cpuid_mask_ecx =3D ~0u; integer_param("cpuid_mask_ecx", opt_cpuid_mask_ecx); unsigned int __devinitdata opt_cpuid_mask_edx =3D ~0u; integer_param("cpuid_mask_edx", opt_cpuid_mask_edx); + +unsigned int __devinitdata opt_cpuid_mask_xsave_eax =3D ~0u; +integer_param("cpuid_mask_ecx", opt_cpuid_mask_xsave_eax); +unsigned int __devinitdata opt_cpuid_mask_xsave_edx =3D ~0u; +integer_param("cpuid_mask_edx", opt_cpuid_mask_xsave_edx); + unsigned int __devinitdata opt_cpuid_mask_ext_ecx =3D ~0u; integer_param("cpuid_mask_ext_ecx", opt_cpuid_mask_ext_ecx); unsigned int __devinitdata opt_cpuid_mask_ext_edx =3D ~0u; --- 2011-04-29.orig/xen/arch/x86/cpu/cpu.h 2010-06-16 12:26:43.0000000= 00 +0200 +++ 2011-04-29/xen/arch/x86/cpu/cpu.h 2011-05-13 10:51:00.000000000 = +0200 @@ -22,6 +22,7 @@ struct cpu_dev { extern struct cpu_dev * cpu_devs [X86_VENDOR_NUM]; =20 extern unsigned int opt_cpuid_mask_ecx, opt_cpuid_mask_edx; +extern unsigned int opt_cpuid_mask_xsave_eax, opt_cpuid_mask_xsave_edx; extern unsigned int opt_cpuid_mask_ext_ecx, opt_cpuid_mask_ext_edx; =20 extern int get_model_name(struct cpuinfo_x86 *c); --- 2011-04-29.orig/xen/arch/x86/cpu/intel.c 2011-03-11 10:13:55.0000000= 00 +0100 +++ 2011-04-29/xen/arch/x86/cpu/intel.c 2011-05-13 10:51:09.000000000 = +0200 @@ -49,9 +49,12 @@ static void __devinit set_cpuidmask(cons wrmsr(MSR_INTEL_CPUID_FEATURE_MASK, opt_cpuid_mask_ecx, opt_cpuid_mask_edx); - if (!~(opt_cpuid_mask_ext_ecx & opt_cpuid_mask_ext_edx)) + if (~(opt_cpuid_mask_ext_ecx & opt_cpuid_mask_ext_edx)) + extra =3D "extended "; + else if (~(opt_cpuid_mask_xsave_eax & opt_cpuid_mask_xsave_= edx)) + extra =3D "xsave "; + else return; - extra =3D "extended "; break; /*=20 * CPU supports this feature if the processor signature meets the = following: @@ -71,11 +74,25 @@ static void __devinit set_cpuidmask(cons wrmsr(MSR_INTEL_CPUID80000001_FEATURE_MASK, opt_cpuid_mask_ext_ecx, opt_cpuid_mask_ext_edx); + if (!~(opt_cpuid_mask_xsave_eax & opt_cpuid_mask_xsave_edx)= ) + return; + extra =3D "xsave "; + break; + case 0x2a: + wrmsr(MSR_INTEL_CPUID1_FEATURE_MASK_V2, + opt_cpuid_mask_ecx, + opt_cpuid_mask_edx); + wrmsr(MSR_INTEL_CPUIDD0_FEATURE_MASK, + opt_cpuid_mask_xsave_eax, + opt_cpuid_mask_xsave_edx); + wrmsr(MSR_INTEL_CPUID80000001_FEATURE_MASK_V2, + opt_cpuid_mask_ext_ecx, + opt_cpuid_mask_ext_edx); return; } =20 - printk(XENLOG_ERR "Cannot set CPU feature mask on CPU#%d\n", - smp_processor_id()); + printk(XENLOG_ERR "Cannot set CPU %sfeature mask on CPU#%d\n", + extra, smp_processor_id()); } =20 void __devinit early_intel_workaround(struct cpuinfo_x86 *c) --- 2011-04-29.orig/xen/include/asm-x86/msr-index.h 2011-01-06 = 16:44:36.000000000 +0100 +++ 2011-04-29/xen/include/asm-x86/msr-index.h 2011-05-12 18:17:28.0000000= 00 +0200 @@ -161,6 +161,10 @@ #define MSR_INTEL_CPUID1_FEATURE_MASK 0x00000130 #define MSR_INTEL_CPUID80000001_FEATURE_MASK 0x00000131 =20 +#define MSR_INTEL_CPUID1_FEATURE_MASK_V2 0x00000132 +#define MSR_INTEL_CPUID80000001_FEATURE_MASK_V2 0x00000133 +#define MSR_INTEL_CPUIDD0_FEATURE_MASK 0x00000134 + /* MSRs & bits used for VMX enabling */ #define MSR_IA32_VMX_BASIC 0x480 #define MSR_IA32_VMX_PINBASED_CTLS 0x481 --=__Part87AB0A60.1__= Content-Type: text/plain; name="x86-intel-flexmigration-v2.patch" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="x86-intel-flexmigration-v2.patch" This follows appnote 485 rev 037, with a slight deviation in the leaf=0A0xd= masking: The document states that ECX and EDX outputs get masked,=0Abut = with the bit fields of interest being in EAX and EDX (while ECX=0Aholds = other information that doesn't make sense to be masked), option=0Aand = variable names use 'eax' instead.=0A=0A(Jun, would be nice if you could = confirm this.)=0A=0ASigned-off-by: Jan Beulich =0A=0A-= -- 2011-04-29.orig/xen/arch/x86/cpu/common.c 2011-04-26 08:19:36.0000000= 00 +0200=0A+++ 2011-04-29/xen/arch/x86/cpu/common.c 2011-05-12 = 18:10:10.000000000 +0200=0A@@ -20,10 +20,17 @@ size_param("cachesize", = cachesize_overri=0A =0A static bool_t __cpuinitdata use_xsave =3D 1;=0A = boolean_param("xsave", use_xsave);=0A+=0A unsigned int __devinitdata = opt_cpuid_mask_ecx =3D ~0u;=0A integer_param("cpuid_mask_ecx", opt_cpuid_ma= sk_ecx);=0A unsigned int __devinitdata opt_cpuid_mask_edx =3D ~0u;=0A = integer_param("cpuid_mask_edx", opt_cpuid_mask_edx);=0A+=0A+unsigned int = __devinitdata opt_cpuid_mask_xsave_eax =3D ~0u;=0A+integer_param("cpuid_mas= k_ecx", opt_cpuid_mask_xsave_eax);=0A+unsigned int __devinitdata opt_cpuid_= mask_xsave_edx =3D ~0u;=0A+integer_param("cpuid_mask_edx", opt_cpuid_mask_x= save_edx);=0A+=0A unsigned int __devinitdata opt_cpuid_mask_ext_ecx =3D = ~0u;=0A integer_param("cpuid_mask_ext_ecx", opt_cpuid_mask_ext_ecx);=0A = unsigned int __devinitdata opt_cpuid_mask_ext_edx =3D ~0u;=0A--- 2011-04-29= .orig/xen/arch/x86/cpu/cpu.h 2010-06-16 12:26:43.000000000 +0200=0A+++ = 2011-04-29/xen/arch/x86/cpu/cpu.h 2011-05-13 10:51:00.000000000 = +0200=0A@@ -22,6 +22,7 @@ struct cpu_dev {=0A extern struct cpu_dev * = cpu_devs [X86_VENDOR_NUM];=0A =0A extern unsigned int opt_cpuid_mask_ecx, = opt_cpuid_mask_edx;=0A+extern unsigned int opt_cpuid_mask_xsave_eax, = opt_cpuid_mask_xsave_edx;=0A extern unsigned int opt_cpuid_mask_ext_ecx, = opt_cpuid_mask_ext_edx;=0A =0A extern int get_model_name(struct cpuinfo_x86= *c);=0A--- 2011-04-29.orig/xen/arch/x86/cpu/intel.c 2011-03-11 = 10:13:55.000000000 +0100=0A+++ 2011-04-29/xen/arch/x86/cpu/intel.c = 2011-05-13 10:51:09.000000000 +0200=0A@@ -49,9 +49,12 @@ static void = __devinit set_cpuidmask(cons=0A wrmsr(MSR_INTEL_CPUID_FEATU= RE_MASK,=0A opt_cpuid_mask_ecx,=0A = opt_cpuid_mask_edx);=0A- if (!~(opt_cpuid_mask_ext_ecx & = opt_cpuid_mask_ext_edx))=0A+ if (~(opt_cpuid_mask_ext_ecx & = opt_cpuid_mask_ext_edx))=0A+ extra =3D "extended ";=0A+ = else if (~(opt_cpuid_mask_xsave_eax & opt_cpuid_mask_xsave_edx))=0A= + extra =3D "xsave ";=0A+ else=0A = return;=0A- extra =3D "extended ";=0A = break;=0A /* =0A * CPU supports this feature if the processor signature = meets the following:=0A@@ -71,11 +74,25 @@ static void __devinit set_cpuidm= ask(cons=0A wrmsr(MSR_INTEL_CPUID80000001_FEATURE_MASK,=0A = opt_cpuid_mask_ext_ecx,=0A opt_cpuid_mask_ext_ed= x);=0A+ if (!~(opt_cpuid_mask_xsave_eax & opt_cpuid_mask_xsave_edx)= )=0A+ return;=0A+ extra =3D "xsave ";=0A+ = break;=0A+ case 0x2a:=0A+ wrmsr(MSR_INTEL_CPUID1_FEATURE_MASK= _V2,=0A+ opt_cpuid_mask_ecx,=0A+ = opt_cpuid_mask_edx);=0A+ wrmsr(MSR_INTEL_CPUIDD0_FEATURE_MAS= K,=0A+ opt_cpuid_mask_xsave_eax,=0A+ = opt_cpuid_mask_xsave_edx);=0A+ wrmsr(MSR_INTEL_CPUID80000001_FEATU= RE_MASK_V2,=0A+ opt_cpuid_mask_ext_ecx,=0A+ = opt_cpuid_mask_ext_edx);=0A return;=0A }=0A =0A- = printk(XENLOG_ERR "Cannot set CPU feature mask on CPU#%d\n",=0A- = smp_processor_id());=0A+ printk(XENLOG_ERR "Cannot set CPU = %sfeature mask on CPU#%d\n",=0A+ extra, smp_processor_id());= =0A }=0A =0A void __devinit early_intel_workaround(struct cpuinfo_x86 = *c)=0A--- 2011-04-29.orig/xen/include/asm-x86/msr-index.h 2011-01-06 = 16:44:36.000000000 +0100=0A+++ 2011-04-29/xen/include/asm-x86/msr-index.h = 2011-05-12 18:17:28.000000000 +0200=0A@@ -161,6 +161,10 @@=0A #define = MSR_INTEL_CPUID1_FEATURE_MASK 0x00000130=0A #define MSR_INTEL_CPUID800000= 01_FEATURE_MASK 0x00000131=0A =0A+#define MSR_INTEL_CPUID1_FEATURE_MASK_V2 = 0x00000132=0A+#define MSR_INTEL_CPUID80000001_FEATURE_MASK_V2 = 0x00000133=0A+#define MSR_INTEL_CPUIDD0_FEATURE_MASK 0x00000134=0A= +=0A /* MSRs & bits used for VMX enabling */=0A #define MSR_IA32_VMX_BASIC = 0x480=0A #define MSR_IA32_VMX_PINBASED_CTLS = 0x481=0A --=__Part87AB0A60.1__= Content-Type: text/plain; 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