From: "Jan Beulich" <JBeulich@novell.com>
To: Andrew Cooper <andrew.cooper3@citrix.com>
Cc: xen devel <xen-devel@lists.xensource.com>
Subject: Re: APIC MSRs query
Date: Tue, 17 May 2011 14:43:53 +0100 [thread overview]
Message-ID: <4DD297B90200007800041A32@vpn.id2.novell.com> (raw)
In-Reply-To: <4DD27760.9020706@citrix.com>
>>> On 17.05.11 at 15:25, Andrew Cooper <andrew.cooper3@citrix.com> wrote:
> Hello,
>
> I am currently cleaning up the APIC code for the sake of
> shutdown/reboot/crashdump and have a query about the (modified for
> brevity) snippet of code:
>
> uint64_t msr_content;
> rdmsrl(MSR_IA32_APICBASE, msr_content);
> msr_content |= MSR_IA32_APICBASE_ENABLE | MSR_IA32_APICBASE_EXTD;
> msr_content = (uint32_t)msr_content;
> wrmsrl(MSR_IA32_APICBASE, msr_content);
>
> which is added into apic.c in changeset b622e411eef8, and has propagated
> elsewhere in the codebase during subsequent cleanups etc.
>
> The MP spec and x2apic spec states that bits [35:12] of
> MSR_IA32_APICBASE is the base APIC MMIO address. Is there reason why
> the code (almost always) clears the top 4 bits, or is it just an
> overlooked mistake?
I think this is a benign mistake. Benign because I don't think there is
a meaningful (to Xen at least) number of systems that would not
have their LAPIC at the default address (which fits in 32 bits).
Jan
next prev parent reply other threads:[~2011-05-17 13:43 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-05-17 13:25 APIC MSRs query Andrew Cooper
2011-05-17 13:43 ` Jan Beulich [this message]
2011-05-17 13:49 ` Andrew Cooper
2011-05-17 13:59 ` Ian Campbell
2011-05-17 14:08 ` Andrew Cooper
2011-05-17 14:08 ` Jan Beulich
2011-05-17 14:53 ` Keir Fraser
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