From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Jan Beulich" Subject: Re: APIC MSRs query Date: Tue, 17 May 2011 14:43:53 +0100 Message-ID: <4DD297B90200007800041A32@vpn.id2.novell.com> References: <4DD27760.9020706@citrix.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: <4DD27760.9020706@citrix.com> Content-Disposition: inline List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: Andrew Cooper Cc: xen devel List-Id: xen-devel@lists.xenproject.org >>> On 17.05.11 at 15:25, Andrew Cooper wrote: > Hello, >=20 > I am currently cleaning up the APIC code for the sake of=20 > shutdown/reboot/crashdump and have a query about the (modified for=20 > brevity) snippet of code: >=20 > uint64_t msr_content; > rdmsrl(MSR_IA32_APICBASE, msr_content); > msr_content |=3D MSR_IA32_APICBASE_ENABLE | MSR_IA32_APICBASE_EXTD; > msr_content =3D (uint32_t)msr_content; > wrmsrl(MSR_IA32_APICBASE, msr_content); >=20 > which is added into apic.c in changeset b622e411eef8, and has propagated= =20 > elsewhere in the codebase during subsequent cleanups etc. >=20 > The MP spec and x2apic spec states that bits [35:12] of=20 > MSR_IA32_APICBASE is the base APIC MMIO address. Is there reason why=20 > the code (almost always) clears the top 4 bits, or is it just an=20 > overlooked mistake? I think this is a benign mistake. Benign because I don't think there is a meaningful (to Xen at least) number of systems that would not have their LAPIC at the default address (which fits in 32 bits). Jan