From mboxrd@z Thu Jan  1 00:00:00 1970
From: Christoph Egger <Christoph.Egger@amd.com>
Subject: [PATCH] nestedsvm: reduce TLB flushes
Date: Wed, 18 May 2011 17:26:06 +0200
Message-ID: <4DD3E50E.4030607@amd.com>
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Reduce TLB flushes:
1. When we update the cr3 during VMRUN/VMEXIT emulation
    we toggle between n1asid and n2asid forth and back
    => no TLB flush needed
2. Only flush n1asid or n2asid depending on vcpu guest mode
    and not both unconditionally.

Signed-off-by: Christoph Egger <Christoph.Egger@amd.com>

-- 
---to satisfy European Law for business letters:
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Registergericht Muenchen, HRB Nr. 43632

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diff -r 0e45a2e91f17 xen/arch/x86/hvm/svm/svm.c
--- a/xen/arch/x86/hvm/svm/svm.c	Thu May 12 14:35:58 2011 +0200
+++ b/xen/arch/x86/hvm/svm/svm.c	Wed May 18 17:26:16 2011 +0200
@@ -450,7 +452,19 @@ static void svm_update_guest_cr(struct v
         break;
     case 3:
         vmcb_set_cr3(vmcb, v->arch.hvm_vcpu.hw_cr[3]);
-        hvm_asid_flush_vcpu(v);
+        if ( !nestedhvm_enabled(v->domain) ) {
+            hvm_asid_flush_vcpu(v);
+            break;
+        }
+        if ( nestedhvm_vmswitch_in_progress(v) )
+            /* During VMRUN/VMEXIT emulation we toggle between
+             * n1asid and n2asid. */
+            break;
+
+        if ( nestedhvm_vcpu_in_guestmode(v) )
+            hvm_asid_flush_vcpu_asid(&vcpu_nestedhvm(v).nv_n2asid);
+        else
+            hvm_asid_flush_vcpu_asid(&v->arch.hvm_vcpu.n1asid);
         break;
     case 4:
         value = HVM_CR4_HOST_MASK;

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