From mboxrd@z Thu Jan 1 00:00:00 1970 From: Wei Huang Subject: Re: Re: [PATCH] x86: clear CPUID output of leaf 0xd for Dom0 when xs Date: Wed, 18 May 2011 15:38:45 -0500 Message-ID: <4DD42E55.60300@amd.com> References: Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0289340693==" Return-path: In-Reply-To: List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: Roger Cruz Cc: "xen-devel@lists.xensource.com" List-Id: xen-devel@lists.xenproject.org --===============0289340693== Content-Type: multipart/alternative; boundary="------------020101090105080807050800" --------------020101090105080807050800 Content-Type: text/plain; charset="ISO-8859-1"; format=flowed Content-Transfer-Encoding: 7bit I think Jan's assumption is correct. All future extension (from either Intel or AMD) will be xsave related. If xsave is disabled, then these extensions should be zapped, not just XSAVEOPT. Regarding sub-leaves of CPUID 0x0D, software is supposed to check CPUID_0xD_subleaf_0[EAX:EDX] before retrieving the values of other sub-leaves. If it doesn't follow this step, software has a benign issue (I don't call it bug). According to spec, cpuid instruction doesn't forbid software to check unsupported CPUID. Returning 0's is enough I think. Regards, -Wei On 05/18/2011 02:58 PM, Roger Cruz wrote: > > Hi Jan, > > I was wondering if we should not let the code fall through and clear > all registers to zero but rather clear just the one bit we care > about? My concern is that a future Intel revision may expand this > function and return other information besides that XSAVEOPT, which > would then be wiped out by the fall-through code. I'm thinking > something like this. Let me know if I have misunderstood something. > > + case 0xd: /* XSAVE */ > + if (!xsave_enabled(current)) > + __clear_bit(X86_FEATURE_XSAVEOPT % 32, &a); > + break; > case 5: /* MONITOR/MWAIT */ > > Roger R. Cruz > > ---------------------- > > Linux starting with 2.6.36 uses the XSAVEOPT instruction and has > certain code paths that look only at the feature bit reported through > CPUID leaf 0xd sub-leaf 1 (i.e. without qualifying the check with one > evaluating leaf 4 output). Consequently the hypervisor ought to mimic > actual hardware in clearing leaf 0xd output when not supporting xsave. > > (Note that this is only a minimal fix. It may be necessary, e.g. for > LWP, to also adjust sub-leaf 0's bit masks and perhaps zap output of > sub-leaves > 1 when the respective bit in sub-leaf 0 is getting > cleared.) > > Signed-off-by: Jan Beulich > > --- a/xen/arch/x86/traps.c > +++ b/xen/arch/x86/traps.c > @@ -836,6 +836,10 @@ static void pv_cpuid(struct cpu_user_reg > __clear_bit(X86_FEATURE_NODEID_MSR % 32, &c); > __clear_bit(X86_FEATURE_TOPOEXT % 32, &c); > break; > + case 0xd: /* XSAVE */ > + if ( xsave_enabled(current) ) > + break; > + /* fall through */ > case 5: /* MONITOR/MWAIT */ > case 0xa: /* Architectural Performance Monitor Features */ > case 0x8000000a: /* SVM revision and features */ > > --------------020101090105080807050800 Content-Type: text/html; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit I think Jan's assumption is correct. All future extension (from either Intel or AMD) will be xsave related. If xsave is disabled, then these extensions should be zapped, not just XSAVEOPT.

Regarding sub-leaves of CPUID 0x0D, software is supposed to check CPUID_0xD_subleaf_0[EAX:EDX] before retrieving the values of other sub-leaves. If it doesn't follow this step, software has a benign issue (I don't call it bug). According to spec, cpuid instruction doesn't forbid software to check unsupported CPUID. Returning 0's is enough I think.

Regards,
-Wei

On 05/18/2011 02:58 PM, Roger Cruz wrote:
Re: [PATCH] x86: clear CPUID output of leaf 0xd for Dom0 when xs

Hi Jan,

I was wondering if we should not let the code fall through and clear all registers to zero but rather clear just the one bit we care about?  My concern is that a future Intel revision may expand this function and return other information besides that XSAVEOPT, which would then be wiped out by the fall-through code.  I'm thinking something like this.  Let me know if I have misunderstood something.

+   case 0xd: /* XSAVE */
+        if (!xsave_enabled(current))
+            __clear_bit(X86_FEATURE_XSAVEOPT % 32, &a);
+        break;
    case 5: /* MONITOR/MWAIT */

Roger R. Cruz

----------------------

Linux starting with 2.6.36 uses the XSAVEOPT instruction and has
certain code paths that look only at the feature bit reported through
CPUID leaf 0xd sub-leaf 1 (i.e. without qualifying the check with one
evaluating leaf 4 output). Consequently the hypervisor ought to mimic
actual hardware in clearing leaf 0xd output when not supporting xsave.

(Note that this is only a minimal fix. It may be necessary, e.g. for
LWP, to also adjust sub-leaf 0's bit masks and perhaps zap output of
sub-leaves > 1 when the respective bit in sub-leaf 0 is getting
cleared.)

Signed-off-by: Jan Beulich <jbeulich@xxxxxxxxxx>

--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -836,6 +836,10 @@ static void pv_cpuid(struct cpu_user_reg
         __clear_bit(X86_FEATURE_NODEID_MSR % 32, &c);
         __clear_bit(X86_FEATURE_TOPOEXT % 32, &c);
         break;
+    case 0xd: /* XSAVE */
+        if ( xsave_enabled(current) )
+            break;
+        /* fall through */
     case 5: /* MONITOR/MWAIT */
     case 0xa: /* Architectural Performance Monitor Features */
     case 0x8000000a: /* SVM revision and features */


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