From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Jan Beulich" Subject: Re: Re: Losing PS/2 Interrupts Date: Mon, 23 May 2011 14:02:31 +0100 Message-ID: <4DDA77070200007800042E74@vpn.id2.novell.com> References: <3E2050B5-59DC-4E4F-9C8D-8C04A6B465EB@gmail.com> <20110520175044.GA30367@dumpdata.com> <5D477258-8216-48BD-8A93-186E044118B9@gmail.com> <4DDA366E0200007800042C71@vpn.id2.novell.com> <1D3BFCDD-9D53-48BA-9ECD-D009AD535C2B@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: <1D3BFCDD-9D53-48BA-9ECD-D009AD535C2B@gmail.com> Content-Disposition: inline List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: Thomas Goetz Cc: Simon Graham , xen-devel@lists.xensource.com, Konrad Rzeszutek Rzeszutek Wilk List-Id: xen-devel@lists.xenproject.org >>> On 23.05.11 at 14:09, Thomas Goetz wrote: > My assumption is that at the point that the i8042 driver reads the = data=20 > register a new interrupt happens. There is gap in time between when the = data=20 > register is read and when the event channel pending state is cleared. = Since=20 > the hypervisor ACKed the previous real interrupt before delivering it to = the=20 > guest, there is nothing to stop the i8042 device from interrupting=20 > immediately after the data register is read. If it interrupt before the = event=20 > channel pending state is cleared, then it will not be delivered to the = guest=20 That would be a bug in the control flow then. In our (non-pvops) kernel we make sure to clear the pending bit *before* calling handle_irq() (and after masking the event channel), which clearly is a requirement at least for edge triggered interrupts (not necessarily before calling handle_irq(), but before calling the device driver's handler, i.e. in chip->ack()). Jan > and the EOI mechanism will be set up, but I haven't found anything in = that=20 > that will set up a delayed delivery of the second interrupt. >=20 > In this situation the i8042 device has every reason to believe the = second=20 > interrupt will be delivered. The previous interrupt was received and = handled.=20 > Nothing is masked. >=20 > Am I missing something? >=20 > --- > Tom Goetz > tcgoetz@gmail.com=20