Re: AMD IOMMU intremap tables and IOAPICs

[Andrew Cooper <andrew.cooper3@citrix.com>]

On 06/09/11 17:06, Tim Deegan wrote:
> At 16:54 +0100 on 06 Sep (1315328056), Andrew Cooper wrote:
>> On 06/09/11 16:47, George Dunlap wrote:
>>> Wei,
>>>
>>> Quick question:  Am I reading the code correctly, that even with
>>> per-device interrupt remap tables, that GSIs are accounted to the
>>> intremap table of the corresponding IOAPIC, presumably because the
>>> IOMMU sees interrupts generated as GSIs as coming from the IOAPIC?  In
>>> that case, then we need all devices sharing the same IOAPIC must not
>>> have any vector collisions.  Is that correct?
>> Based on the ICH10 IO-APIC documentation with respect to auto EOIs, we
>> cant have any two IRQs across any IO-APICs sharing a vector,
>> irrespective of IOMMU or not.  (Because the EOI'ing an IO-APIC entry
>> only takes account of vector and not destination)
> If this is the case, is there any point in having per-CPU IDTs?  
> Or per-device remapping tables?
>
> Tim.

My understanding is:

GSIs should always have unique vectors (due to the auto EOI broadcast)
AMD IOMMU with per-device remapping tables means that devices cant ever
share interrupts when migrating.
AMD IOMMU with a global remapping table negates the benefit of per-CPU IDTs

Therefore per-CPU IDTs are useful, but there is juggling required when
choosing a new vector on migrate (With the possibility of having free
vectors, but unable to assign any because of other restrictions)

-- 
Andrew Cooper - Dom0 Kernel Engineer, Citrix XenServer
T: +44 (0)1223 225 900, http://www.citrix.com