From mboxrd@z Thu Jan 1 00:00:00 1970 From: Christoph Egger Subject: Re: [PATCH] Xen/MCE: adjust for future new vMCE model Date: Thu, 5 Jul 2012 11:18:43 +0200 Message-ID: <4FF55BF3.5000500@amd.com> References: <4FF4444D.5040304@amd.com> <4FF557A4020000780008DC60@nat28.tlf.novell.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <4FF557A4020000780008DC60@nat28.tlf.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Jan Beulich Cc: Jinsong Liu , "xen-devel@lists.xensource.com" , Keir Fraser , Ian Campbell , Yunhong Jiang , Will Auld , Tony Luck List-Id: xen-devel@lists.xenproject.org On 07/05/12 09:00, Jan Beulich wrote: >>>> On 04.07.12 at 18:08, "Liu, Jinsong" wrote: >> Christoph Egger wrote: >>> On 07/04/12 15:08, Liu, Jinsong wrote: >>>> + g_mcg_cap = MCG_TES_P | MCG_SER_P | GUEST_BANK_NUM; >>>> + >>> >>> >>> Is MCG_TES_P and MCG_SER_P emulated independent if the host has them >>> or not? For AMD this only works if the answer is yes. >>> >>> (I know in upstream this code path is used by Intel only but I have >>> patches that brings this code path in use by both AMD and Intel.) >>> >>> Christoph >> >> I'm not sure if AMD has these 2 bits in MCG_CAP. Could you tell me where can >> I get AMD's *latest* open doc (something like amd architecture programmer >> manual)? >> >> If AMD has these 2 bits, it's safe to set them independent of host >> capability -- guest will just think it running on a platform w/ some events >> *possilbe* (though actually may never occur), hypervisor know what actually >> occur and has the flexibility to decide what it would like to inject to >> guest. > > According to the latest doc I have access to, neither of these two > bits are known there (nor are any other of the bits beyond 8). But > as we don't want to surface model specific behavior to guests, > having these bits set seems the right thing in any case. The > MCi_STATUS values reported to guests just may need some > additional massaging. > > All this is of course assuming that AMD won't assign these bits > _different_ meanings in the future, but as that would be pretty > counter productive (requiring more vendor specific code in all OSes) > that seems pretty unlikely. Christoph? Let me ask back internally. Christoph -- ---to satisfy European Law for business letters: Advanced Micro Devices GmbH Einsteinring 24, 85689 Dornach b. Muenchen Geschaeftsfuehrer: Alberto Bozzo, Andrew Bowd Sitz: Dornach, Gemeinde Aschheim, Landkreis Muenchen Registergericht Muenchen, HRB Nr. 43632