From: Andre Przywara <andre.przywara@linaro.org>
To: Julien Grall <julien.grall@linaro.org>,
Stefano Stabellini <sstabellini@kernel.org>
Cc: xen-devel@lists.xenproject.org
Subject: Re: [PATCH v3 6/8] ARM: VGIC: factor out vgic_get_hw_irq_desc()
Date: Wed, 31 Jan 2018 16:24:14 +0000 [thread overview]
Message-ID: <4e43fe67-2618-0085-fd9b-f0209afa7983@linaro.org> (raw)
In-Reply-To: <41c4cb64-9504-f52d-56c3-1acc89e64c12@linaro.org>
Hi,
On 31/01/18 16:16, Julien Grall wrote:
> Hi,
>
> On 24/01/18 18:10, Andre Przywara wrote:
>> At the moment we happily access the VGIC internal struct pending_irq
>> (which describes a virtual IRQ) in irq.c.
>> Factor out the actually needed functionality to learn the associated
>> hardware IRQ and move that into gic-vgic.c to improve abstraction.
>>
>> Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
>> Acked-by: Stefano Stabellini <sstabellini@kernel.org>
>> ---
>> xen/arch/arm/gic-vgic.c | 15 +++++++++++++++
>> xen/arch/arm/irq.c | 7 ++-----
>> xen/include/asm-arm/vgic.h | 2 ++
>> 3 files changed, 19 insertions(+), 5 deletions(-)
>>
>> diff --git a/xen/arch/arm/gic-vgic.c b/xen/arch/arm/gic-vgic.c
>> index d44e4dacd3..3ad98dcd3a 100644
>> --- a/xen/arch/arm/gic-vgic.c
>> +++ b/xen/arch/arm/gic-vgic.c
>> @@ -411,6 +411,21 @@ void gic_dump_vgic_info(struct vcpu *v)
>> printk("Pending irq=%d\n", p->irq);
>> }
>> +struct irq_desc *vgic_get_hw_irq_desc(struct domain *d, struct vcpu
>> *v,
>> + unsigned int virq)
>> +{
>> + struct pending_irq *p;
>> +
>> + if ( !v )
>> + v = d->vcpu[0];
>
> I dislike this new function in the current state. Let's imagine someone
> decide to pass a PPI but no vCPU. The vCPU would now be default to vCPU0
> and potentially returning the wrong irq_desc (imagine PPI passthrough
> such as for the vtimer).
>
> So the code needs at least checking the vCPU is passed in the case of a
> PPI. I would be happy with an ASSERT().
Yeah, good point. Something like ASSERT(!v && virq >= 32), I guess?
Cheers,
Andre.
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next prev parent reply other threads:[~2018-01-31 16:24 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-24 18:10 [PATCH v3 0/8] ARM: VGIC/GIC separation cleanups Andre Przywara
2018-01-24 18:10 ` [PATCH v3 1/8] ARM: VGIC: drop unneeded gic_restore_pending_irqs() Andre Przywara
2018-01-30 11:48 ` Julien Grall
2018-01-30 17:26 ` Stefano Stabellini
2018-01-24 18:10 ` [PATCH v3 2/8] ARM: VGIC: split gic.c to observe hardware/virtual GIC separation Andre Przywara
2018-01-30 11:53 ` Julien Grall
2018-01-24 18:10 ` [PATCH v3 3/8] ARM: VGIC: split up gic_dump_info() to cover virtual part separately Andre Przywara
2018-01-24 18:10 ` [PATCH v3 4/8] ARM: VGIC: rework events_need_delivery() Andre Przywara
2018-01-24 18:10 ` [PATCH v3 5/8] ARM: VGIC: factor out vgic_connect_hw_irq() Andre Przywara
2018-01-30 13:19 ` Julien Grall
2018-01-31 15:54 ` Andre Przywara
2018-01-31 16:30 ` Julien Grall
2018-02-01 12:07 ` Andre Przywara
2018-01-24 18:10 ` [PATCH v3 6/8] ARM: VGIC: factor out vgic_get_hw_irq_desc() Andre Przywara
2018-01-31 16:16 ` Julien Grall
2018-01-31 16:24 ` Andre Przywara [this message]
2018-01-31 16:25 ` Julien Grall
2018-01-24 18:10 ` [PATCH v3 7/8] ARM: VGIC: rework gicv[23]_update_lr to not use pending_irq Andre Przywara
2018-01-24 18:10 ` [PATCH v3 8/8] ARM: make nr_irqs a constant Andre Przywara
2018-01-30 13:24 ` Julien Grall
2018-01-30 14:36 ` Roger Pau Monné
2018-02-01 13:43 ` Andre Przywara
2018-02-01 13:47 ` Julien Grall
2018-02-01 14:34 ` Andre Przywara
2018-02-01 14:39 ` Julien Grall
2018-02-01 14:41 ` Andre Przywara
2018-02-01 13:57 ` Roger Pau Monné
2018-02-01 14:39 ` Andre Przywara
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