From: Mohit Gambhir <mohit.gambhir@oracle.com>
To: Andrew Cooper <andrew.cooper3@citrix.com>, xen-devel@lists.xen.org
Cc: boris.ostrovsky@oracle.com
Subject: Re: [PATCH v3 1/2][XTF] xtf/vpmu: Add Intel PMU MSR addresses
Date: Tue, 25 Apr 2017 13:46:47 -0400 [thread overview]
Message-ID: <4fbd817c-b49f-09db-fc3e-6a21f9983ed6@oracle.com> (raw)
In-Reply-To: <e512c1a1-c153-0c06-9d1b-e80dd43aea40@citrix.com>
On 04/25/2017 11:24 AM, Andrew Cooper wrote:
> On 24/04/17 18:54, Mohit Gambhir wrote:
>> This patch adds Intel PMU MSR addresses as macros for VPMU testing
>>
>> Signed-off-by: Mohit Gambhir <mohit.gambhir@oracle.com>
>> ---
>> arch/x86/include/arch/msr-index.h | 11 +++++++++++
>> 1 file changed, 11 insertions(+)
>>
>> diff --git a/arch/x86/include/arch/msr-index.h b/arch/x86/include/arch/msr-index.h
>> index 2e90079..3a79025 100644
>> --- a/arch/x86/include/arch/msr-index.h
>> +++ b/arch/x86/include/arch/msr-index.h
>> @@ -38,6 +38,17 @@
>> #define MSR_GS_BASE 0xc0000101
>> #define MSR_SHADOW_GS_BASE 0xc0000102
>>
>> +#define MSR_IA32_PMC(n) (0x000000c1 + (n))
>> +#define MSR_IA32_PERFEVTSEL(n) (0x00000186 + (n))
>> +#define MSR_IA32_DEBUGCTL 0x000001d9
> I have just recently pushed the LBR/TSX test case, which adds DEBUGCTL.
OK
>> +#define MSR_IA32_FIXED_CTR(n) (0x00000309 + (n))
>> +#define MSR_IA32_PERF_CAPABILITIES 0x00000345
>> +#define MSR_IA32_FIXED_CTR_CTRL 0x0000038d
>> +#define MSR_IA32_PERF_GLOBAL_CTRL 0x0000038f
>> +#define MSR_IA32_PERF_GLOBAL_STATUS 0x0000038e
>> +#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390
>> +#define MSR_IA32_A_PMC(n) (0x000004c1 + (n))
> Please drop the IA32 infixes. They only add extra clutter. Please also
> keep the entire file sorted by MSR index, which will require splitting
> this block into two.
OK
> What is the difference between (what will be) MSR_PMC() and MSR_A_PMC() ?
MSR_A_PMCx are alias addresses to MSR_PMCx that are used for full-width
read/write access while
MSR_PMCx can only be used for 32 bit read/writes. You can take a look at
Intel SDM Vol 3B section 18.2.5
"Full-Width Write to Performance Counter Registers" for details.
>
> ~Andrew
>
> _______________________________________________
> Xen-devel mailing list
> Xen-devel@lists.xen.org
> https://lists.xen.org/xen-devel
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next prev parent reply other threads:[~2017-04-25 17:46 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-04-24 17:54 [PATCH v3 0/2][XTF] xtf/vpmu VPMU tests Mohit Gambhir
2017-04-24 17:54 ` [PATCH v3 1/2][XTF] xtf/vpmu: Add Intel PMU MSR addresses Mohit Gambhir
2017-04-25 8:36 ` Jan Beulich
2017-04-25 15:04 ` Mohit Gambhir
2017-04-25 15:24 ` Andrew Cooper
2017-04-25 17:46 ` Mohit Gambhir [this message]
2017-04-26 6:07 ` Jan Beulich
2017-04-26 8:02 ` Andrew Cooper
2017-04-24 17:54 ` [PATCH v3 2/2][XTF] xtf/vpmu: MSR read/write tests for VPMU Mohit Gambhir
2017-04-25 18:20 ` Andrew Cooper
2017-04-25 21:45 ` Mohit Gambhir
2017-05-03 20:41 ` Andrew Cooper
2017-05-04 21:13 ` Mohit Gambhir
2017-05-04 21:36 ` Mohit Gambhir
2017-04-25 18:50 ` [PATCH v3 0/2][XTF] xtf/vpmu VPMU tests Andrew Cooper
2017-04-28 19:35 ` Mohit Gambhir
2017-05-03 20:07 ` Andrew Cooper
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