* [PATCH] Dump IOMMU p2m table
@ 2012-08-14 19:55 Santosh Jodh
2012-08-15 8:54 ` Jan Beulich
0 siblings, 1 reply; 13+ messages in thread
From: Santosh Jodh @ 2012-08-14 19:55 UTC (permalink / raw)
To: xen-devel; +Cc: wei.wang2, tim, xiantao.zhang
New key handler 'o' to dump the IOMMU p2m table for each domain.
Skips dumping table for domain0.
Intel and AMD specific iommu_ops handler for dumping p2m table.
Signed-off-by: Santosh Jodh<santosh.jodh@citrix.com>
diff -r dc56a9defa30 -r 5357dccf4ba3 xen/drivers/passthrough/amd/pci_amd_iommu.c
--- a/xen/drivers/passthrough/amd/pci_amd_iommu.c Tue Aug 14 10:28:14 2012 +0200
+++ b/xen/drivers/passthrough/amd/pci_amd_iommu.c Tue Aug 14 12:54:55 2012 -0700
@@ -22,6 +22,7 @@
#include <xen/pci.h>
#include <xen/pci_regs.h>
#include <xen/paging.h>
+#include <xen/softirq.h>
#include <asm/hvm/iommu.h>
#include <asm/amd-iommu.h>
#include <asm/hvm/svm/amd-iommu-proto.h>
@@ -512,6 +513,72 @@ static int amd_iommu_group_id(u16 seg, u
#include <asm/io_apic.h>
+static void amd_dump_p2m_table_level(struct page_info* pg, int level,
+ paddr_t gpa, int indent)
+{
+ paddr_t address;
+ void *table_vaddr, *pde;
+ paddr_t next_table_maddr;
+ int index, next_level, present;
+ u32 *entry;
+
+ if ( level < 1 )
+ return;
+
+ table_vaddr = __map_domain_page(pg);
+ if ( table_vaddr == NULL )
+ {
+ printk("Failed to map IOMMU domain page %"PRIpaddr"\n",
+ page_to_maddr(pg));
+ return;
+ }
+
+ for ( index = 0; index < PTE_PER_TABLE_SIZE; index++ )
+ {
+ if ( !(index % 2) )
+ process_pending_softirqs();
+
+ pde = table_vaddr + (index * IOMMU_PAGE_TABLE_ENTRY_SIZE);
+ next_table_maddr = amd_iommu_get_next_table_from_pte(pde);
+ entry = (u32*)pde;
+
+ present = get_field_from_reg_u32(entry[0],
+ IOMMU_PDE_PRESENT_MASK,
+ IOMMU_PDE_PRESENT_SHIFT);
+
+ if ( !present )
+ continue;
+
+ next_level = get_field_from_reg_u32(entry[0],
+ IOMMU_PDE_NEXT_LEVEL_MASK,
+ IOMMU_PDE_NEXT_LEVEL_SHIFT);
+
+ address = gpa + amd_offset_level_address(index, level);
+ if ( next_level >= 1 )
+ amd_dump_p2m_table_level(
+ maddr_to_page(next_table_maddr), level - 1,
+ address, indent + 1);
+ else
+ printk("%*s" "gfn: %08lx mfn: %08lx\n",
+ indent, " ",
+ (unsigned long)PFN_DOWN(address),
+ (unsigned long)PFN_DOWN(next_table_maddr));
+ }
+
+ unmap_domain_page(table_vaddr);
+}
+
+static void amd_dump_p2m_table(struct domain *d)
+{
+ struct hvm_iommu *hd = domain_hvm_iommu(d);
+
+ if ( !hd->root_table )
+ return;
+
+ printk("p2m table has %d levels\n", hd->paging_mode);
+ amd_dump_p2m_table_level(hd->root_table, hd->paging_mode, 0, 0);
+}
+
const struct iommu_ops amd_iommu_ops = {
.init = amd_iommu_domain_init,
.dom0_init = amd_iommu_dom0_init,
@@ -531,4 +598,5 @@ const struct iommu_ops amd_iommu_ops = {
.resume = amd_iommu_resume,
.share_p2m = amd_iommu_share_p2m,
.crash_shutdown = amd_iommu_suspend,
+ .dump_p2m_table = amd_dump_p2m_table,
};
diff -r dc56a9defa30 -r 5357dccf4ba3 xen/drivers/passthrough/iommu.c
--- a/xen/drivers/passthrough/iommu.c Tue Aug 14 10:28:14 2012 +0200
+++ b/xen/drivers/passthrough/iommu.c Tue Aug 14 12:54:55 2012 -0700
@@ -19,10 +19,12 @@
#include <xen/paging.h>
#include <xen/guest_access.h>
#include <xen/softirq.h>
+#include <xen/keyhandler.h>
#include <xsm/xsm.h>
static void parse_iommu_param(char *s);
static int iommu_populate_page_table(struct domain *d);
+static void iommu_dump_p2m_table(unsigned char key);
/*
* The 'iommu' parameter enables the IOMMU. Optional comma separated
@@ -54,6 +56,12 @@ bool_t __read_mostly amd_iommu_perdev_in
DEFINE_PER_CPU(bool_t, iommu_dont_flush_iotlb);
+static struct keyhandler iommu_p2m_table = {
+ .diagnostic = 0,
+ .u.fn = iommu_dump_p2m_table,
+ .desc = "dump iommu p2m table"
+};
+
static void __init parse_iommu_param(char *s)
{
char *ss;
@@ -119,6 +127,7 @@ void __init iommu_dom0_init(struct domai
if ( !iommu_enabled )
return;
+ register_keyhandler('o', &iommu_p2m_table);
d->need_iommu = !!iommu_dom0_strict;
if ( need_iommu(d) )
{
@@ -654,6 +663,34 @@ int iommu_do_domctl(
return ret;
}
+static void iommu_dump_p2m_table(unsigned char key)
+{
+ struct domain *d;
+ const struct iommu_ops *ops;
+
+ if ( !iommu_enabled )
+ {
+ printk("IOMMU not enabled!\n");
+ return;
+ }
+
+ ops = iommu_get_ops();
+ for_each_domain(d)
+ {
+ if ( !d->domain_id )
+ continue;
+
+ if ( iommu_use_hap_pt(d) )
+ {
+ printk("\ndomain%d IOMMU p2m table shared with MMU: \n", d->domain_id);
+ continue;
+ }
+
+ printk("\ndomain%d IOMMU p2m table: \n", d->domain_id);
+ ops->dump_p2m_table(d);
+ }
+}
+
/*
* Local variables:
* mode: C
diff -r dc56a9defa30 -r 5357dccf4ba3 xen/drivers/passthrough/vtd/iommu.c
--- a/xen/drivers/passthrough/vtd/iommu.c Tue Aug 14 10:28:14 2012 +0200
+++ b/xen/drivers/passthrough/vtd/iommu.c Tue Aug 14 12:54:55 2012 -0700
@@ -31,6 +31,7 @@
#include <xen/pci.h>
#include <xen/pci_regs.h>
#include <xen/keyhandler.h>
+#include <xen/softirq.h>
#include <asm/msi.h>
#include <asm/irq.h>
#if defined(__i386__) || defined(__x86_64__)
@@ -2365,6 +2366,63 @@ static void vtd_resume(void)
}
}
+static void vtd_dump_p2m_table_level(paddr_t pt_maddr, int level, paddr_t gpa,
+ int indent)
+{
+ paddr_t address;
+ int i;
+ struct dma_pte *pt_vaddr, *pte;
+ int next_level;
+
+ if ( level < 1 )
+ return;
+
+ pt_vaddr = map_vtd_domain_page(pt_maddr);
+ if ( pt_vaddr == NULL )
+ {
+ printk("Failed to map VT-D domain page %"PRIpaddr"\n", pt_maddr);
+ return;
+ }
+
+ next_level = level - 1;
+ for ( i = 0; i < PTE_NUM; i++ )
+ {
+ if ( !(i % 2) )
+ process_pending_softirqs();
+
+ pte = &pt_vaddr[i];
+ if ( !dma_pte_present(*pte) )
+ continue;
+
+ address = gpa + offset_level_address(i, level);
+ if ( next_level >= 1 )
+ vtd_dump_p2m_table_level(dma_pte_addr(*pte), next_level,
+ address, indent + 1);
+ else
+ printk("%*s" "gfn: %08lx mfn: %08lx super=%d rd=%d wr=%d\n",
+ indent, " ",
+ (unsigned long)(address >> PAGE_SHIFT_4K),
+ (unsigned long)(pte->val >> PAGE_SHIFT_4K),
+ dma_pte_superpage(*pte)? 1 : 0,
+ dma_pte_read(*pte)? 1 : 0,
+ dma_pte_write(*pte)? 1 : 0);
+ }
+
+ unmap_vtd_domain_page(pt_vaddr);
+}
+
+static void vtd_dump_p2m_table(struct domain *d)
+{
+ struct hvm_iommu *hd;
+
+ if ( list_empty(&acpi_drhd_units) )
+ return;
+
+ hd = domain_hvm_iommu(d);
+ printk("p2m table has %d levels\n", agaw_to_level(hd->agaw));
+ vtd_dump_p2m_table_level(hd->pgd_maddr, agaw_to_level(hd->agaw), 0, 0);
+}
+
const struct iommu_ops intel_iommu_ops = {
.init = intel_iommu_domain_init,
.dom0_init = intel_iommu_dom0_init,
@@ -2387,6 +2445,7 @@ const struct iommu_ops intel_iommu_ops =
.crash_shutdown = vtd_crash_shutdown,
.iotlb_flush = intel_iommu_iotlb_flush,
.iotlb_flush_all = intel_iommu_iotlb_flush_all,
+ .dump_p2m_table = vtd_dump_p2m_table,
};
/*
diff -r dc56a9defa30 -r 5357dccf4ba3 xen/drivers/passthrough/vtd/iommu.h
--- a/xen/drivers/passthrough/vtd/iommu.h Tue Aug 14 10:28:14 2012 +0200
+++ b/xen/drivers/passthrough/vtd/iommu.h Tue Aug 14 12:54:55 2012 -0700
@@ -248,6 +248,8 @@ struct context_entry {
#define level_to_offset_bits(l) (12 + (l - 1) * LEVEL_STRIDE)
#define address_level_offset(addr, level) \
((addr >> level_to_offset_bits(level)) & LEVEL_MASK)
+#define offset_level_address(offset, level) \
+ ((u64)(offset) << level_to_offset_bits(level))
#define level_mask(l) (((u64)(-1)) << level_to_offset_bits(l))
#define level_size(l) (1 << level_to_offset_bits(l))
#define align_to_level(addr, l) ((addr + level_size(l) - 1) & level_mask(l))
@@ -277,6 +279,9 @@ struct dma_pte {
#define dma_set_pte_addr(p, addr) do {\
(p).val |= ((addr) & PAGE_MASK_4K); } while (0)
#define dma_pte_present(p) (((p).val & 3) != 0)
+#define dma_pte_superpage(p) (((p).val & (1<<7)) != 0)
+#define dma_pte_read(p) (((p).val & DMA_PTE_READ) != 0)
+#define dma_pte_write(p) (((p).val & DMA_PTE_WRITE) != 0)
/* interrupt remap entry */
struct iremap_entry {
diff -r dc56a9defa30 -r 5357dccf4ba3 xen/include/asm-x86/hvm/svm/amd-iommu-defs.h
--- a/xen/include/asm-x86/hvm/svm/amd-iommu-defs.h Tue Aug 14 10:28:14 2012 +0200
+++ b/xen/include/asm-x86/hvm/svm/amd-iommu-defs.h Tue Aug 14 12:54:55 2012 -0700
@@ -38,6 +38,10 @@
#define PTE_PER_TABLE_ALLOC(entries) \
PAGE_SIZE * (PTE_PER_TABLE_ALIGN(entries) >> PTE_PER_TABLE_SHIFT)
+#define amd_offset_level_address(offset, level) \
+ ((u64)(offset) << (12 + (PTE_PER_TABLE_SHIFT * \
+ (level - IOMMU_PAGING_MODE_LEVEL_1))))
+
#define PCI_MIN_CAP_OFFSET 0x40
#define PCI_MAX_CAP_BLOCKS 48
#define PCI_CAP_PTR_MASK 0xFC
diff -r dc56a9defa30 -r 5357dccf4ba3 xen/include/xen/iommu.h
--- a/xen/include/xen/iommu.h Tue Aug 14 10:28:14 2012 +0200
+++ b/xen/include/xen/iommu.h Tue Aug 14 12:54:55 2012 -0700
@@ -141,6 +141,7 @@ struct iommu_ops {
void (*crash_shutdown)(void);
void (*iotlb_flush)(struct domain *d, unsigned long gfn, unsigned int page_count);
void (*iotlb_flush_all)(struct domain *d);
+ void (*dump_p2m_table)(struct domain *d);
};
void iommu_update_ire_from_apic(unsigned int apic, unsigned int reg, unsigned int value);
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] Dump IOMMU p2m table
2012-08-14 19:55 Santosh Jodh
@ 2012-08-15 8:54 ` Jan Beulich
2012-08-15 10:39 ` Wei Wang
2012-08-16 16:27 ` Santosh Jodh
0 siblings, 2 replies; 13+ messages in thread
From: Jan Beulich @ 2012-08-15 8:54 UTC (permalink / raw)
To: Santosh Jodh; +Cc: wei.wang2, tim, xiantao.zhang, xen-devel
>>> On 14.08.12 at 21:55, Santosh Jodh <santosh.jodh@citrix.com> wrote:
Sorry to be picky; after this many rounds I would have
expected that no further comments would be needed.
> +static void amd_dump_p2m_table_level(struct page_info* pg, int level,
> + paddr_t gpa, int indent)
> +{
> + paddr_t address;
> + void *table_vaddr, *pde;
> + paddr_t next_table_maddr;
> + int index, next_level, present;
> + u32 *entry;
> +
> + if ( level < 1 )
> + return;
> +
> + table_vaddr = __map_domain_page(pg);
> + if ( table_vaddr == NULL )
> + {
> + printk("Failed to map IOMMU domain page %"PRIpaddr"\n",
> + page_to_maddr(pg));
> + return;
> + }
> +
> + for ( index = 0; index < PTE_PER_TABLE_SIZE; index++ )
> + {
> + if ( !(index % 2) )
> + process_pending_softirqs();
> +
> + pde = table_vaddr + (index * IOMMU_PAGE_TABLE_ENTRY_SIZE);
> + next_table_maddr = amd_iommu_get_next_table_from_pte(pde);
> + entry = (u32*)pde;
> +
> + present = get_field_from_reg_u32(entry[0],
> + IOMMU_PDE_PRESENT_MASK,
> + IOMMU_PDE_PRESENT_SHIFT);
> +
> + if ( !present )
> + continue;
> +
> + next_level = get_field_from_reg_u32(entry[0],
> + IOMMU_PDE_NEXT_LEVEL_MASK,
> + IOMMU_PDE_NEXT_LEVEL_SHIFT);
> +
> + address = gpa + amd_offset_level_address(index, level);
> + if ( next_level >= 1 )
> + amd_dump_p2m_table_level(
> + maddr_to_page(next_table_maddr), level - 1,
Did you see Wei's cleanup patches to the code you cloned from?
You should follow that route (replacing the ASSERT() with
printing of the inconsistency and _not_ recursing or doing the
normal printing), and using either "level" or "next_level"
consistently here.
> + address, indent + 1);
> + else
> + printk("%*s" "gfn: %08lx mfn: %08lx\n",
> + indent, " ",
printk("%*sgfn: %08lx mfn: %08lx\n",
indent, "",
I can vaguely see the point in splitting the two strings in the
first argument, but the extra space in the third argument is
definitely wrong - it'll make level 1 and level 2 indistinguishable.
I also don't see how you addressed Wei's reporting of this still
not printing correctly. I may be overlooking something, but
without you making clear in the description what you changed
over the previous version that's also relatively easy to happen.
> +static void vtd_dump_p2m_table_level(paddr_t pt_maddr, int level, paddr_t gpa,
> + int indent)
> +{
> + paddr_t address;
> + int i;
> + struct dma_pte *pt_vaddr, *pte;
> + int next_level;
> +
> + if ( level < 1 )
> + return;
> +
> + pt_vaddr = map_vtd_domain_page(pt_maddr);
> + if ( pt_vaddr == NULL )
> + {
> + printk("Failed to map VT-D domain page %"PRIpaddr"\n", pt_maddr);
> + return;
> + }
> +
> + next_level = level - 1;
> + for ( i = 0; i < PTE_NUM; i++ )
> + {
> + if ( !(i % 2) )
> + process_pending_softirqs();
> +
> + pte = &pt_vaddr[i];
> + if ( !dma_pte_present(*pte) )
> + continue;
> +
> + address = gpa + offset_level_address(i, level);
> + if ( next_level >= 1 )
> + vtd_dump_p2m_table_level(dma_pte_addr(*pte), next_level,
> + address, indent + 1);
> + else
> + printk("%*s" "gfn: %08lx mfn: %08lx super=%d rd=%d wr=%d\n",
> + indent, " ",
Same comment as above.
> + (unsigned long)(address >> PAGE_SHIFT_4K),
> + (unsigned long)(pte->val >> PAGE_SHIFT_4K),
> + dma_pte_superpage(*pte)? 1 : 0,
> + dma_pte_read(*pte)? 1 : 0,
> + dma_pte_write(*pte)? 1 : 0);
Missing spaces. Even worse - given your definitions of these
macros there's no point in using the conditional operators here
at all.
And, despite your claim in another response, this still isn't similar
to AMD's variant (which still doesn't print any of these three
attributes).
The printing of the superpage status is pretty pointless anyway,
given that there's no single use of dma_set_pte_superpage()
throughout the tree - validly so since superpages can be in use
currently only when the tables are shared with EPT, in which
case you don't print anything. Plus you'd need to detect the flag
_above_ level 1 (at leaf level the bit is ignored and hence just
confusing if printed) and print the entry instead of recursing. And
if you decide to indeed properly implement this (rather than just
dropping superpage support here), _I_ would expect you to
properly implement level skipping in the corresponding AMD code
too (which similarly isn't being used currently).
Jan
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] Dump IOMMU p2m table
2012-08-15 8:54 ` Jan Beulich
@ 2012-08-15 10:39 ` Wei Wang
2012-08-16 16:27 ` Santosh Jodh
1 sibling, 0 replies; 13+ messages in thread
From: Wei Wang @ 2012-08-15 10:39 UTC (permalink / raw)
To: Jan Beulich; +Cc: tim, xiantao.zhang, Santosh Jodh, xen-devel
[-- Attachment #1: Type: text/plain, Size: 6240 bytes --]
On 08/15/2012 10:54 AM, Jan Beulich wrote:
>>>> On 14.08.12 at 21:55, Santosh Jodh<santosh.jodh@citrix.com> wrote:
>
> Sorry to be picky; after this many rounds I would have
> expected that no further comments would be needed.
>
>> +static void amd_dump_p2m_table_level(struct page_info* pg, int level,
>> + paddr_t gpa, int indent)
>> +{
>> + paddr_t address;
>> + void *table_vaddr, *pde;
>> + paddr_t next_table_maddr;
>> + int index, next_level, present;
>> + u32 *entry;
>> +
>> + if ( level< 1 )
>> + return;
>> +
>> + table_vaddr = __map_domain_page(pg);
>> + if ( table_vaddr == NULL )
>> + {
>> + printk("Failed to map IOMMU domain page %"PRIpaddr"\n",
>> + page_to_maddr(pg));
>> + return;
>> + }
>> +
>> + for ( index = 0; index< PTE_PER_TABLE_SIZE; index++ )
>> + {
>> + if ( !(index % 2) )
>> + process_pending_softirqs();
>> +
>> + pde = table_vaddr + (index * IOMMU_PAGE_TABLE_ENTRY_SIZE);
>> + next_table_maddr = amd_iommu_get_next_table_from_pte(pde);
>> + entry = (u32*)pde;
>> +
>> + present = get_field_from_reg_u32(entry[0],
>> + IOMMU_PDE_PRESENT_MASK,
>> + IOMMU_PDE_PRESENT_SHIFT);
>> +
>> + if ( !present )
>> + continue;
>> +
>> + next_level = get_field_from_reg_u32(entry[0],
>> + IOMMU_PDE_NEXT_LEVEL_MASK,
>> + IOMMU_PDE_NEXT_LEVEL_SHIFT);
>> +
>> + address = gpa + amd_offset_level_address(index, level);
>> + if ( next_level>= 1 )
>> + amd_dump_p2m_table_level(
>> + maddr_to_page(next_table_maddr), level - 1,
>
> Did you see Wei's cleanup patches to the code you cloned from?
> You should follow that route (replacing the ASSERT() with
> printing of the inconsistency and _not_ recursing or doing the
> normal printing), and using either "level" or "next_level"
> consistently here.
Hi, I tested the patch and the output looks much better now，please see
attachment. One thing I notice: there is a 1GB mapping in the guest, but
the format of it looks like other 2MB mappings:
(XEN) gfn: 0003fa00 mfn: 0023b000
(XEN) gfn: 0003fc00 mfn: 00136200
(XEN) gfn: 0003fe00 mfn: 0023ae00
(XEN) gfn: 00040000 mfn: 00040000 << 1GB here
(XEN) gfn: 00080000 mfn: 0023ac00
(XEN) gfn: 00080200 mfn: 00136000
(XEN) gfn: 00080400 mfn: 0023aa00
(XEN) gfn: 00080600 mfn: 00135e00
(XEN) gfn: 00080800 mfn: 0023a800
(XEN) gfn: 00080a00 mfn: 00135c00
(XEN) gfn: 00080c00 mfn: 0023a600
(XEN) gfn: 00080e00 mfn: 00135a00
(XEN) gfn: 00081000 mfn: 0023a400
(XEN) gfn: 00081200 mfn: 00135800
(XEN) gfn: 00081400 mfn: 0023a200
(XEN) gfn: 00081600 mfn: 00135600
Thanks,
Wei
>> + address, indent + 1);
>> + else
>> + printk("%*s" "gfn: %08lx mfn: %08lx\n",
>> + indent, " ",
>
> printk("%*sgfn: %08lx mfn: %08lx\n",
> indent, "",
>
> I can vaguely see the point in splitting the two strings in the
> first argument, but the extra space in the third argument is
> definitely wrong - it'll make level 1 and level 2 indistinguishable.
>
> I also don't see how you addressed Wei's reporting of this still
> not printing correctly. I may be overlooking something, but
> without you making clear in the description what you changed
> over the previous version that's also relatively easy to happen.
>
>> +static void vtd_dump_p2m_table_level(paddr_t pt_maddr, int level, paddr_t gpa,
>> + int indent)
>> +{
>> + paddr_t address;
>> + int i;
>> + struct dma_pte *pt_vaddr, *pte;
>> + int next_level;
>> +
>> + if ( level< 1 )
>> + return;
>> +
>> + pt_vaddr = map_vtd_domain_page(pt_maddr);
>> + if ( pt_vaddr == NULL )
>> + {
>> + printk("Failed to map VT-D domain page %"PRIpaddr"\n", pt_maddr);
>> + return;
>> + }
>> +
>> + next_level = level - 1;
>> + for ( i = 0; i< PTE_NUM; i++ )
>> + {
>> + if ( !(i % 2) )
>> + process_pending_softirqs();
>> +
>> + pte =&pt_vaddr[i];
>> + if ( !dma_pte_present(*pte) )
>> + continue;
>> +
>> + address = gpa + offset_level_address(i, level);
>> + if ( next_level>= 1 )
>> + vtd_dump_p2m_table_level(dma_pte_addr(*pte), next_level,
>> + address, indent + 1);
>> + else
>> + printk("%*s" "gfn: %08lx mfn: %08lx super=%d rd=%d wr=%d\n",
>> + indent, " ",
>
> Same comment as above.
>
>> + (unsigned long)(address>> PAGE_SHIFT_4K),
>> + (unsigned long)(pte->val>> PAGE_SHIFT_4K),
>> + dma_pte_superpage(*pte)? 1 : 0,
>> + dma_pte_read(*pte)? 1 : 0,
>> + dma_pte_write(*pte)? 1 : 0);
>
> Missing spaces. Even worse - given your definitions of these
> macros there's no point in using the conditional operators here
> at all.
>
> And, despite your claim in another response, this still isn't similar
> to AMD's variant (which still doesn't print any of these three
> attributes).
>
> The printing of the superpage status is pretty pointless anyway,
> given that there's no single use of dma_set_pte_superpage()
> throughout the tree - validly so since superpages can be in use
> currently only when the tables are shared with EPT, in which
> case you don't print anything. Plus you'd need to detect the flag
> _above_ level 1 (at leaf level the bit is ignored and hence just
> confusing if printed) and print the entry instead of recursing. And
> if you decide to indeed properly implement this (rather than just
> dropping superpage support here), _I_ would expect you to
> properly implement level skipping in the corresponding AMD code
> too (which similarly isn't being used currently).
>
> Jan
>
[-- Attachment #2: io_pt.dump --]
[-- Type: text/plain, Size: 109711 bytes --]
(XEN) HVM2: int13_harddisk: function 41, unmapped device for ELDL=81
(XEN) HVM2: int13_harddisk: function 08, unmapped device for ELDL=81
(XEN) HVM2: *** int 15h function AX=00c0, BX=0000 not yet supported!
(XEN)
(XEN) domain2 IOMMU p2m table:
(XEN) p2m table has 3 levels
(XEN) gfn: 00000000 mfn: 00218f00
(XEN) gfn: 00000001 mfn: 001019e1
(XEN) gfn: 00000002 mfn: 00218eff
(XEN) gfn: 00000003 mfn: 00102e66
(XEN) gfn: 00000004 mfn: 00218efe
(XEN) gfn: 00000005 mfn: 00102bea
(XEN) gfn: 00000006 mfn: 00218efd
(XEN) gfn: 00000007 mfn: 00101352
(XEN) gfn: 00000008 mfn: 00218efc
(XEN) gfn: 00000009 mfn: 00101c8f
(XEN) gfn: 0000000a mfn: 00218efb
(XEN) gfn: 0000000b mfn: 00101a5f
(XEN) gfn: 0000000c mfn: 00218efa
(XEN) gfn: 0000000d mfn: 001018f9
(XEN) gfn: 0000000e mfn: 00218ef9
(XEN) gfn: 0000000f mfn: 001004c9
(XEN) gfn: 00000010 mfn: 00218ef8
(XEN) gfn: 00000011 mfn: 00102708
(XEN) gfn: 00000012 mfn: 00218ef7
(XEN) gfn: 00000013 mfn: 00101900
(XEN) gfn: 00000014 mfn: 00218ef6
(XEN) gfn: 00000015 mfn: 00102510
(XEN) gfn: 00000016 mfn: 00218ef5
(XEN) gfn: 00000017 mfn: 00101dd1
(XEN) gfn: 00000018 mfn: 00218ef4
(XEN) gfn: 00000019 mfn: 00102726
(XEN) gfn: 0000001a mfn: 00218ef3
(XEN) gfn: 0000001b mfn: 0010198a
(XEN) gfn: 0000001c mfn: 00218ef2
(XEN) gfn: 0000001d mfn: 001026e9
(XEN) gfn: 0000001e mfn: 00218ef1
(XEN) gfn: 0000001f mfn: 0010297f
(XEN) gfn: 00000020 mfn: 00218ef0
(XEN) gfn: 00000021 mfn: 00102eb3
(XEN) gfn: 00000022 mfn: 00218eef
(XEN) gfn: 00000023 mfn: 0010051f
(XEN) gfn: 00000024 mfn: 00218eee
(XEN) gfn: 00000025 mfn: 00102931
(XEN) gfn: 00000026 mfn: 00218eed
(XEN) gfn: 00000027 mfn: 00101891
(XEN) gfn: 00000028 mfn: 00218eec
(XEN) gfn: 00000029 mfn: 001013ff
(XEN) gfn: 0000002a mfn: 00218eeb
(XEN) gfn: 0000002b mfn: 001014b1
(XEN) gfn: 0000002c mfn: 00218eea
(XEN) gfn: 0000002d mfn: 00101a74
(XEN) gfn: 0000002e mfn: 00218ee9
(XEN) gfn: 0000002f mfn: 0010273e
(XEN) gfn: 00000030 mfn: 00218ee8
(XEN) gfn: 00000031 mfn: 0010284b
(XEN) gfn: 00000032 mfn: 00218ee7
(XEN) gfn: 00000033 mfn: 001014fd
(XEN) gfn: 00000034 mfn: 00218ee6
(XEN) gfn: 00000035 mfn: 0010055e
(XEN) gfn: 00000036 mfn: 00218ee5
(XEN) gfn: 00000037 mfn: 0010134e
(XEN) gfn: 00000038 mfn: 00218ee4
(XEN) gfn: 00000039 mfn: 00101488
(XEN) gfn: 0000003a mfn: 00218ee3
(XEN) gfn: 0000003b mfn: 00101310
(XEN) gfn: 0000003c mfn: 00218ee2
(XEN) gfn: 0000003d mfn: 0010188e
(XEN) gfn: 0000003e mfn: 00218ee1
(XEN) gfn: 0000003f mfn: 0010286e
(XEN) gfn: 00000040 mfn: 00218ee0
(XEN) gfn: 00000041 mfn: 0010187e
(XEN) gfn: 00000042 mfn: 00218edf
(XEN) gfn: 00000043 mfn: 0010030e
(XEN) gfn: 00000044 mfn: 00218ede
(XEN) gfn: 00000045 mfn: 00100498
(XEN) gfn: 00000046 mfn: 00218edd
(XEN) gfn: 00000047 mfn: 00102dd0
(XEN) gfn: 00000048 mfn: 00218edc
(XEN) gfn: 00000049 mfn: 00102dda
(XEN) gfn: 0000004a mfn: 00218edb
(XEN) gfn: 0000004b mfn: 00101770
(XEN) gfn: 0000004c mfn: 00218eda
(XEN) gfn: 0000004d mfn: 00102cb5
(XEN) gfn: 0000004e mfn: 00218ed9
(XEN) gfn: 0000004f mfn: 00102e9a
(XEN) gfn: 00000050 mfn: 00218ed8
(XEN) gfn: 00000051 mfn: 00101829
(XEN) gfn: 00000052 mfn: 00218ed7
(XEN) gfn: 00000053 mfn: 00102991
(XEN) gfn: 00000054 mfn: 00218ed6
(XEN) gfn: 00000055 mfn: 0010157c
(XEN) gfn: 00000056 mfn: 00218ed5
(XEN) gfn: 00000057 mfn: 001017c3
(XEN) gfn: 00000058 mfn: 00218ed4
(XEN) gfn: 00000059 mfn: 00102a42
(XEN) gfn: 0000005a mfn: 00218ed3
(XEN) gfn: 0000005b mfn: 00101a8f
(XEN) gfn: 0000005c mfn: 00218ed2
(XEN) gfn: 0000005d mfn: 00102a69
(XEN) gfn: 0000005e mfn: 00218ed1
(XEN) gfn: 0000005f mfn: 0010181d
(XEN) gfn: 00000060 mfn: 00218ed0
(XEN) gfn: 00000061 mfn: 00101ac7
(XEN) gfn: 00000062 mfn: 00218ecf
(XEN) gfn: 00000063 mfn: 001014da
(XEN) gfn: 00000064 mfn: 00218ece
(XEN) gfn: 00000065 mfn: 00101a0c
(XEN) gfn: 00000066 mfn: 00218ecd
(XEN) gfn: 00000067 mfn: 001028c6
(XEN) gfn: 00000068 mfn: 00218ecc
(XEN) gfn: 00000069 mfn: 00102a1a
(XEN) gfn: 0000006a mfn: 00218ecb
(XEN) gfn: 0000006b mfn: 00102446
(XEN) gfn: 0000006c mfn: 00218eca
(XEN) gfn: 0000006d mfn: 00101383
(XEN) gfn: 0000006e mfn: 00218ec9
(XEN) gfn: 0000006f mfn: 00102cc2
(XEN) gfn: 00000070 mfn: 00218ec8
(XEN) gfn: 00000071 mfn: 00101deb
(XEN) gfn: 00000072 mfn: 00218ec7
(XEN) gfn: 00000073 mfn: 001021a8
(XEN) gfn: 00000074 mfn: 00218ec6
(XEN) gfn: 00000075 mfn: 001002fb
(XEN) gfn: 00000076 mfn: 00218ec5
(XEN) gfn: 00000077 mfn: 001014cc
(XEN) gfn: 00000078 mfn: 00218ec4
(XEN) gfn: 00000079 mfn: 00101544
(XEN) gfn: 0000007a mfn: 00218ec3
(XEN) gfn: 0000007b mfn: 00101d9f
(XEN) gfn: 0000007c mfn: 00218ec2
(XEN) gfn: 0000007d mfn: 00101a88
(XEN) gfn: 0000007e mfn: 00218ec1
(XEN) gfn: 0000007f mfn: 00101a60
(XEN) gfn: 00000080 mfn: 00218ec0
(XEN) gfn: 00000081 mfn: 00102915
(XEN) gfn: 00000082 mfn: 00218ebf
(XEN) gfn: 00000083 mfn: 00101301
(XEN) gfn: 00000084 mfn: 00218ebe
(XEN) gfn: 00000085 mfn: 001015d8
(XEN) gfn: 00000086 mfn: 00218ebd
(XEN) gfn: 00000087 mfn: 001018ad
(XEN) gfn: 00000088 mfn: 00218ebc
(XEN) gfn: 00000089 mfn: 00101533
(XEN) gfn: 0000008a mfn: 00218ebb
(XEN) gfn: 0000008b mfn: 00101ed4
(XEN) gfn: 0000008c mfn: 00218eba
(XEN) gfn: 0000008d mfn: 00101a01
(XEN) gfn: 0000008e mfn: 00218eb9
(XEN) gfn: 0000008f mfn: 0010159e
(XEN) gfn: 00000090 mfn: 00218eb8
(XEN) gfn: 00000091 mfn: 00102571
(XEN) gfn: 00000092 mfn: 00218eb7
(XEN) gfn: 00000093 mfn: 00102cfe
(XEN) gfn: 00000094 mfn: 00218eb6
(XEN) gfn: 00000095 mfn: 0010055d
(XEN) gfn: 00000096 mfn: 00218eb5
(XEN) gfn: 00000097 mfn: 00102d27
(XEN) gfn: 00000098 mfn: 00218eb4
(XEN) gfn: 00000099 mfn: 001027c6
(XEN) gfn: 0000009a mfn: 00218eb3
(XEN) gfn: 0000009b mfn: 001014af
(XEN) gfn: 0000009c mfn: 00218eb2
(XEN) gfn: 0000009d mfn: 00102e76
(XEN) gfn: 0000009e mfn: 00218eb1
(XEN) gfn: 0000009f mfn: 0010235e
(XEN) gfn: 00000100 mfn: 00218e90
(XEN) gfn: 00000101 mfn: 0010171e
(XEN) gfn: 00000102 mfn: 00218e8f
(XEN) gfn: 00000103 mfn: 00102eb1
(XEN) gfn: 00000104 mfn: 00218e8e
(XEN) gfn: 00000105 mfn: 001019d2
(XEN) gfn: 00000106 mfn: 00218e8d
(XEN) gfn: 00000107 mfn: 00100310
(XEN) gfn: 00000108 mfn: 00218e8c
(XEN) gfn: 00000109 mfn: 00101817
(XEN) gfn: 0000010a mfn: 00218e8b
(XEN) gfn: 0000010b mfn: 0010187b
(XEN) gfn: 0000010c mfn: 00218e8a
(XEN) gfn: 0000010d mfn: 00101a53
(XEN) gfn: 0000010e mfn: 00218e89
(XEN) gfn: 0000010f mfn: 00102997
(XEN) gfn: 00000110 mfn: 00218e88
(XEN) gfn: 00000111 mfn: 00101504
(XEN) gfn: 00000112 mfn: 00218e87
(XEN) gfn: 00000113 mfn: 00101a98
(XEN) gfn: 00000114 mfn: 00218e86
(XEN) gfn: 00000115 mfn: 00102832
(XEN) gfn: 00000116 mfn: 00218e85
(XEN) gfn: 00000117 mfn: 00101ec3
(XEN) gfn: 00000118 mfn: 00218e84
(XEN) gfn: 00000119 mfn: 00102e1f
(XEN) gfn: 0000011a mfn: 00218e83
(XEN) gfn: 0000011b mfn: 001003a8
(XEN) gfn: 0000011c mfn: 00218e82
(XEN) gfn: 0000011d mfn: 00101e73
(XEN) gfn: 0000011e mfn: 00218e81
(XEN) gfn: 0000011f mfn: 001026ed
(XEN) gfn: 00000120 mfn: 00218e80
(XEN) gfn: 00000121 mfn: 00100567
(XEN) gfn: 00000122 mfn: 00218e7f
(XEN) gfn: 00000123 mfn: 001014f2
(XEN) gfn: 00000124 mfn: 00218e7e
(XEN) gfn: 00000125 mfn: 001002ed
(XEN) gfn: 00000126 mfn: 00218e7d
(XEN) gfn: 00000127 mfn: 001018ba
(XEN) gfn: 00000128 mfn: 00218e7c
(XEN) gfn: 00000129 mfn: 00101375
(XEN) gfn: 0000012a mfn: 00218e7b
(XEN) gfn: 0000012b mfn: 001013ea
(XEN) gfn: 0000012c mfn: 00218e7a
(XEN) gfn: 0000012d mfn: 001018de
(XEN) gfn: 0000012e mfn: 00218e79
(XEN) gfn: 0000012f mfn: 00100570
(XEN) gfn: 00000130 mfn: 00218e78
(XEN) gfn: 00000131 mfn: 0010143e
(XEN) gfn: 00000132 mfn: 00218e77
(XEN) gfn: 00000133 mfn: 0010136a
(XEN) gfn: 00000134 mfn: 00218e76
(XEN) gfn: 00000135 mfn: 001013a5
(XEN) gfn: 00000136 mfn: 00218e75
(XEN) gfn: 00000137 mfn: 001027f5
(XEN) gfn: 00000138 mfn: 00218e74
(XEN) gfn: 00000139 mfn: 00102a49
(XEN) gfn: 0000013a mfn: 00218e73
(XEN) gfn: 0000013b mfn: 00101dc7
(XEN) gfn: 0000013c mfn: 00218e72
(XEN) gfn: 0000013d mfn: 00102d60
(XEN) gfn: 0000013e mfn: 00218e71
(XEN) gfn: 0000013f mfn: 001015a2
(XEN) gfn: 00000140 mfn: 00218e70
(XEN) gfn: 00000141 mfn: 0010277b
(XEN) gfn: 00000142 mfn: 00218e6f
(XEN) gfn: 00000143 mfn: 001028af
(XEN) gfn: 00000144 mfn: 00218e6e
(XEN) gfn: 00000145 mfn: 0010194f
(XEN) gfn: 00000146 mfn: 00218e6d
(XEN) gfn: 00000147 mfn: 00101a63
(XEN) gfn: 00000148 mfn: 00218e6c
(XEN) gfn: 00000149 mfn: 00101541
(XEN) gfn: 0000014a mfn: 00218e6b
(XEN) gfn: 0000014b mfn: 00102dcc
(XEN) gfn: 0000014c mfn: 00218e6a
(XEN) gfn: 0000014d mfn: 0010281c
(XEN) gfn: 0000014e mfn: 00218e69
(XEN) gfn: 0000014f mfn: 00102e32
(XEN) gfn: 00000150 mfn: 00218e68
(XEN) gfn: 00000151 mfn: 001004c4
(XEN) gfn: 00000152 mfn: 00218e67
(XEN) gfn: 00000153 mfn: 00102c18
(XEN) gfn: 00000154 mfn: 00218e66
(XEN) gfn: 00000155 mfn: 00102c17
(XEN) gfn: 00000156 mfn: 00218e65
(XEN) gfn: 00000157 mfn: 00101dd8
(XEN) gfn: 00000158 mfn: 00218e64
(XEN) gfn: 00000159 mfn: 00101dd7
(XEN) gfn: 0000015a mfn: 00218e63
(XEN) gfn: 0000015b mfn: 001027bf
(XEN) gfn: 0000015c mfn: 00218e62
(XEN) gfn: 0000015d mfn: 00100534
(XEN) gfn: 0000015e mfn: 00218e61
(XEN) gfn: 0000015f mfn: 00102e96
(XEN) gfn: 00000160 mfn: 00218e60
(XEN) gfn: 00000161 mfn: 001014ca
(XEN) gfn: 00000162 mfn: 00218e5f
(XEN) gfn: 00000163 mfn: 001014c9
(XEN) gfn: 00000164 mfn: 00218e5e
(XEN) gfn: 00000165 mfn: 00102e2a
(XEN) gfn: 00000166 mfn: 00218e5d
(XEN) gfn: 00000167 mfn: 00102e29
(XEN) gfn: 00000168 mfn: 00218e5c
(XEN) gfn: 00000169 mfn: 00102465
(XEN) gfn: 0000016a mfn: 00218e5b
(XEN) gfn: 0000016b mfn: 00102e84
(XEN) gfn: 0000016c mfn: 00218e5a
(XEN) gfn: 0000016d mfn: 00102e83
(XEN) gfn: 0000016e mfn: 00218e59
(XEN) gfn: 0000016f mfn: 00102757
(XEN) gfn: 00000170 mfn: 00218e58
(XEN) gfn: 00000171 mfn: 00101492
(XEN) gfn: 00000172 mfn: 00218e57
(XEN) gfn: 00000173 mfn: 00102a10
(XEN) gfn: 00000174 mfn: 00218e56
(XEN) gfn: 00000175 mfn: 00102a0f
(XEN) gfn: 00000176 mfn: 00218e55
(XEN) gfn: 00000177 mfn: 00102ec4
(XEN) gfn: 00000178 mfn: 00218e54
(XEN) gfn: 00000179 mfn: 00102ec3
(XEN) gfn: 0000017a mfn: 00218e53
(XEN) gfn: 0000017b mfn: 00102a5a
(XEN) gfn: 0000017c mfn: 00218e52
(XEN) gfn: 0000017d mfn: 00102a59
(XEN) gfn: 0000017e mfn: 00218e51
(XEN) gfn: 0000017f mfn: 0010130e
(XEN) gfn: 00000180 mfn: 00218e50
(XEN) gfn: 00000181 mfn: 001018b4
(XEN) gfn: 00000182 mfn: 00218e4f
(XEN) gfn: 00000183 mfn: 001018b3
(XEN) gfn: 00000184 mfn: 00218e4e
(XEN) gfn: 00000185 mfn: 0010247e
(XEN) gfn: 00000186 mfn: 00218e4d
(XEN) gfn: 00000187 mfn: 00101394
(XEN) gfn: 00000188 mfn: 00218e4c
(XEN) gfn: 00000189 mfn: 00101393
(XEN) gfn: 0000018a mfn: 00218e4b
(XEN) gfn: 0000018b mfn: 00102dd6
(XEN) gfn: 0000018c m+fn: 00218e4a
(XEN) gfn: 0000018d mfn: 00102dd5
(XEN) gfn: 0000018e mfn: 00218e49
(XEN) gfn: 0000018f mfn: 00102994
(XEN) gfn: 00000190 mfn: 00218e48
(XEN) gfn: 00000191 mfn: 00102993
(XEN) gfn: 00000192 mfn: 00218e47
(XEN) gfn: 00000193 mfn: 00102de2
(XEN) gfn: 00000194 mfn: 00218e46
(XEN) gfn: 00000195 mfn: 00102de1
(XEN) gfn: 00000196 mfn: 00218e45
(XEN) gfn: 00000197 mfn: 00101713
(XEN) gfn: 00000198 mfn: 00218e44
(XEN) gfn: 00000199 mfn: 0010139a
(XEN) gfn: 0000019a mfn: 00218e43
(XEN) gfn: 0000019b mfn: 00102c26
(XEN) gfn: 0000019c mfn: 00218e42
(XEN) gfn: 0000019d mfn: 00102c25
(XEN) gfn: 0000019e mfn: 00218e41
(XEN) gfn: 0000019f mfn: 00101448
(XEN) gfn: 000001a0 mfn: 00218e40
(XEN) gfn: 000001a1 mfn: 00101447
(XEN) gfn: 000001a2 mfn: 00218e3f
(XEN) gfn: 000001a3 mfn: 00101e84
(XEN) gfn: 000001a4 mfn: 00218e3e
(XEN) gfn: 000001a5 mfn: 001013a7
(XEN) gfn: 000001a6 mfn: 00218e3d
(XEN) gfn: 000001a7 mfn: 00102def
(XEN) gfn: 000001a8 mfn: 00218e3c
(XEN) gfn: 000001a9 mfn: 001012db
(XEN) gfn: 000001aa mfn: 00218e3b
(XEN) gfn: 000001ab mfn: 00100524
(XEN) gfn: 000001ac mfn: 00218e3a
(XEN) gfn: 000001ad mfn: 00100523
(XEN) gfn: 000001ae mfn: 00218e39
(XEN) gfn: 000001af mfn: 00102e08
(XEN) gfn: 000001b0 mfn: 00218e38
(XEN) gfn: 000001b1 mfn: 00102e07
(XEN) gfn: 000001b2 mfn: 00218e37
(XEN) gfn: 000001b3 mfn: 00102881
(XEN) gfn: 000001b4 mfn: 00218e36
(XEN) gfn: 000001b5 mfn: 00102946
(XEN) gfn: 000001b6 mfn: 00218e35
(XEN) gfn: 000001b7 mfn: 00100357
(XEN) gfn: 000001b8 mfn: 00218e34
(XEN) gfn: 000001b9 mfn: 00101876
(XEN) gfn: 000001ba mfn: 00218e33
(XEN) gfn: 000001bb mfn: 00101875
(XEN) gfn: 000001bc mfn: 00218e32
(XEN) gfn: 000001bd mfn: 0010148c
(XEN) gfn: 000001be mfn: 00218e31
(XEN) gfn: 000001bf mfn: 0010148b
(XEN) gfn: 000001c0 mfn: 00218e30
(XEN) gfn: 000001c1 mfn: 0010189a
(XEN) gfn: 000001c2 mfn: 00218e2f
(XEN) gfn: 000001c3 mfn: 00101899
(XEN) gfn: 000001c4 mfn: 00218e2e
(XEN) gfn: 000001c5 mfn: 00101858
(XEN) gfn: 000001c6 mfn: 00218e2d
(XEN) gfn: 000001c7 mfn: 00101857
(XEN) gfn: 000001c8 mfn: 00218e2c
(XEN) gfn: 000001c9 mfn: 00102de6
(XEN) gfn: 000001ca mfn: 00218e2b
(XEN) gfn: 000001cb mfn: 00102de5
(XEN) gfn: 000001cc mfn: 00218e2a
(XEN) gfn: 000001cd mfn: 0010175d
(XEN) gfn: 000001ce mfn: 00218e29
(XEN) gfn: 000001cf mfn: 0010175c
(XEN) gfn: 000001d0 mfn: 00218e28
(XEN) gfn: 000001d1 mfn: 00102c53
(XEN) gfn: 000001d2 mfn: 00218e27
(XEN) gfn: 000001d3 mfn: 00102c52
(XEN) gfn: 000001d4 mfn: 00218e26
(XEN) gfn: 000001d5 mfn: 00101741
(XEN) gfn: 000001d6 mfn: 00218e25
(XEN) gfn: 000001d7 mfn: 00101740
(XEN) gfn: 000001d8 mfn: 00218e24
(XEN) gfn: 000001d9 mfn: 0010286b
(XEN) gfn: 000001da mfn: 00218e23
(XEN) gfn: 000001db mfn: 0010286a
(XEN) gfn: 000001dc mfn: 00218e22
(XEN) gfn: 000001dd mfn: 00101805
(XEN) gfn: 000001de mfn: 00218e21
(XEN) gfn: 000001df mfn: 00101804
(XEN) gfn: 000001e0 mfn: 00218e20
(XEN) gfn: 000001e1 mfn: 00101803
(XEN) gfn: 000001e2 mfn: 00218e1f
(XEN) gfn: 000001e3 mfn: 00101802
(XEN) gfn: 000001e4 mfn: 00218e1e
(XEN) gfn: 000001e5 mfn: 0010287b
(XEN) gfn: 000001e6 mfn: 00218e1d
(XEN) gfn: 000001e7 mfn: 0010287a
(XEN) gfn: 000001e8 mfn: 00218e1c
(XEN) gfn: 000001e9 mfn: 001027bb
(XEN) gfn: 000001ea mfn: 00218e1b
(XEN) gfn: 000001eb mfn: 001027ba
(XEN) gfn: 000001ec mfn: 00218e1a
(XEN) gfn: 000001ed mfn: 00102cfb
(XEN) gfn: 000001ee mfn: 00218e19
(XEN) gfn: 000001ef mfn: 00102cfa
(XEN) gfn: 000001f0 mfn: 00218e18
(XEN) gfn: 000001f1 mfn: 00101e37
(XEN) gfn: 000001f2 mfn: 00218e17
(XEN) gfn: 000001f3 mfn: 00101e36
(XEN) gfn: 000001f4 mfn: 00218e16
(XEN) gfn: 000001f5 mfn: 00101aaf
(XEN) gfn: 000001f6 mfn: 00218e15
(XEN) gfn: 000001f7 mfn: 00101aae
(XEN) gfn: 000001f8 mfn: 00218e14
(XEN) gfn: 000001f9 mfn: 00101a6f
(XEN) gfn: 000001fa mfn: 00218e13
(XEN) gfn: 000001fb mfn: 00101a6e
(XEN) gfn: 000001fc mfn: 00218e12
(XEN) gfn: 000001fd mfn: 00101a43
(XEN) gfn: 000001fe mfn: 00218e11
(XEN) gfn: 000001ff mfn: 00101a42
(XEN) gfn: 00000200 mfn: 00218c00
(XEN) gfn: 00000400 mfn: 0010be00
(XEN) gfn: 00000600 mfn: 00218a00
(XEN) gfn: 00000800 mfn: 0010bc00
(XEN) gfn: 00000a00 mfn: 00218800
(XEN) gfn: 00000c00 mfn: 0010ba00
(XEN) gfn: 00000e00 mfn: 00218600
(XEN) gfn: 00001000 mfn: 0010b800
(XEN) gfn: 00001200 mfn: 00218400
(XEN) gfn: 00001400 mfn: 0010b600
(XEN) gfn: 00001600 mfn: 00218200
(XEN) gfn: 00001800 mfn: 0010b400
(XEN) gfn: 00001a00 mfn: 00218000
(XEN) gfn: 00001c00 mfn: 0010b200
(XEN) gfn: 00001e00 mfn: 0021fe00
(XEN) gfn: 00002000 mfn: 0010b000
(XEN) gfn: 00002200 mfn: 0021fc00
(XEN) gfn: 00002400 mfn: 0010ae00
(XEN) gfn: 00002600 mfn: 0021fa00
(XEN) gfn: 00002800 mfn: 0010ac00
(XEN) gfn: 00002a00 mfn: 0021f800
(XEN) gfn: 00002c00 mfn: 0010aa00
(XEN) gfn: 00002e00 mfn: 0021f600
(XEN) gfn: 00003000 mfn: 0010a800
(XEN) gfn: 00003200 mfn: 0021f400
(XEN) gfn: 00003400 mfn: 0010a600
(XEN) gfn: 00003600 mfn: 0021f200
(XEN) gfn: 00003800 mfn: 0010a400
(XEN) gfn: 00003a00 mfn: 0021f000
(XEN) gfn: 00003c00 mfn: 0010a200
(XEN) gfn: 00003e00 mfn: 0021ee00
(XEN) gfn: 00004000 mfn: 0010a000
(XEN) gfn: 00004200 mfn: 0021ec00
(XEN) gfn: 00004400 mfn: 0010fe00
(XEN) gfn: 00004600 mfn: 0021ea00
(XEN) gfn: 00004800 mfn: 0010fc00
(XEN) gfn: 00004a00 mfn: 0021e800
(XEN) gfn: 00004c00 mfn: 0010fa00
(XEN) gfn: 00004e00 mfn: 0021e600
(XEN) gfn: 00005000 mfn: 0010f800
(XEN) gfn: 00005200 mfn: 0021e400
(XEN) gfn: 00005400 mfn: 0010f600
(XEN) gfn: 00005600 mfn: 0021e200
(XEN) gfn: 00005800 mfn: 0010f400
(XEN) gfn: 00005a00 mfn: 0021e000
(XEN) gfn: 00005c00 mfn: 0010f200
(XEN) gfn: 00005e00 mfn: 00217e00
(XEN) gfn: 00006000 mfn: 0010f000
(XEN) gfn: 00006200 mfn: 00217c00
(XEN) gfn: 00006400 mfn: 0010ee00
(XEN) gfn: 00006600 mfn: 00217a00
(XEN) gfn: 00006800 mfn: 0010ec00
(XEN) gfn: 00006a00 mfn: 00217800
(XEN) gfn: 00006c00 mfn: 0010ea00
(XEN) gfn: 00006e00 mfn: 00217600
(XEN) gfn: 00007000 mfn: 0010e800
(XEN) gfn: 00007200 mfn: 00217400
(XEN) gfn: 00007400 mfn: 0010e600
(XEN) gfn: 00007600 mfn: 00217200
(XEN) gfn: 00007800 mfn: 0010e400
(XEN) gfn: 00007a00 mfn: 00217000
(XEN) gfn: 00007c00 mfn: 0010e200
(XEN) gfn: 00007e00 mfn: 00216e00
(XEN) gfn: 00008000 mfn: 0010e000
(XEN) gfn: 00008200 mfn: 00216c00
(XEN) gfn: 00008400 mfn: 0010de00
(XEN) gfn: 00008600 mfn: 00216a00
(XEN) gfn: 00008800 mfn: 0010dc00
(XEN) gfn: 00008a00 mfn: 00216800
(XEN) gfn: 00008c00 mfn: 0010da00
(XEN) gfn: 00008e00 mfn: 00216600
(XEN) gfn: 00009000 mfn: 0010d800
(XEN) gfn: 00009200 mfn: 00216400
(XEN) gfn: 00009400 mfn: 0010d600
(XEN) gfn: 00009600 mfn: 00216200
(XEN) gfn: 00009800 mfn: 0010d400
(XEN) gfn: 00009a00 mfn: 00216000
(XEN) gfn: 00009c00 mfn: 0010d200
(XEN) gfn: 00009e00 mfn: 00215e00
(XEN) gfn: 0000a000 mfn: 0010d000
(XEN) gfn: 0000a200 mfn: 00215c00
(XEN) gfn: 0000a400 mfn: 0010ce00
(XEN) gfn: 0000a600 mfn: 00215a00
(XEN) gfn: 0000a800 mfn: 0010cc00
(XEN) gfn: 0000aa00 mfn: 00215800
(XEN) gfn: 0000ac00 mfn: 0010ca00
(XEN) gfn: 0000ae00 mfn: 00215600
(XEN) gfn: 0000b000 mfn: 0010c800
(XEN) gfn: 0000b200 mfn: 00215400
(XEN) gfn: 0000b400 mfn: 0010c600
(XEN) gfn: 0000b600 mfn: 00215200
(XEN) gfn: 0000b800 mfn: 0010c400
(XEN) gfn: 0000ba00 mfn: 00215000
(XEN) gfn: 0000bc00 mfn: 0010c200
(XEN) gfn: 0000be00 mfn: 00214e00
(XEN) gfn: 0000c000 mfn: 0010c000
(XEN) gfn: 0000c200 mfn: 00214c00
(XEN) gfn: 0000c400 mfn: 0011fe00
(XEN) gfn: 0000c600 mfn: 00214a00
(XEN) gfn: 0000c800 mfn: 0011fc00
(XEN) gfn: 0000ca00 mfn: 00214800
(XEN) gfn: 0000cc00 mfn: 0011fa00
(XEN) gfn: 0000ce00 mfn: 00214600
(XEN) gfn: 0000d000 mfn: 0011f800
(XEN) gfn: 0000d200 mfn: 00214400
(XEN) gfn: 0000d400 mfn: 0011f600
(XEN) gfn: 0000d600 mfn: 00214200
(XEN) gfn: 0000d800 mfn: 0011f400
(XEN) gfn: 0000da00 mfn: 00214000
(XEN) gfn: 0000dc00 mfn: 0011f200
(XEN) gfn: 0000de00 mfn: 00213e00
(XEN) gfn: 0000e000 mfn: 0011f000
(XEN) gfn: 0000e200 mfn: 00213c00
(XEN) gfn: 0000e400 mfn: 0011ee00
(XEN) gfn: 0000e600 mfn: 00213a00
(XEN) gfn: 0000e800 mfn: 0011ec00
(XEN) gfn: 0000ea00 mfn: 00213800
(XEN) gfn: 0000ec00 mfn: 0011ea00
(XEN) gfn: 0000ee00 mfn: 00213600
(XEN) gfn: 0000f000 mfn: 0011e800
(XEN) gfn: 0000f200 mfn: 00213400
(XEN) gfn: 0000f400 mfn: 0011e600
(XEN) gfn: 0000f600 mfn: 00213200
(XEN) gfn: 0000f800 mfn: 0011e400
(XEN) gfn: 0000fa00 mfn: 00213000
(XEN) gfn: 0000fc00 mfn: 0011e200
(XEN) gfn: 0000fe00 mfn: 00212e00
(XEN) gfn: 00010000 mfn: 0011e000
(XEN) gfn: 00010200 mfn: 00212c00
(XEN) gfn: 00010400 mfn: 0011de00
(XEN) gfn: 00010600 mfn: 00212a00
(XEN) gfn: 00010800 mfn: 0011dc00
(XEN) gfn: 00010a00 mfn: 00212800
(XEN) gfn: 00010c00 mfn: 0011da00
(XEN) gfn: 00010e00 mfn: 00212600
(XEN) gfn: 00011000 mfn: 0011d800
(XEN) gfn: 00011200 mfn: 00212400
(XEN) gfn: 00011400 mfn: 0011d600
(XEN) gfn: 00011600 mfn: 00212200
(XEN) gfn: 00011800 mfn: 0011d400
(XEN) gfn: 00011a00 mfn: 00212000
(XEN) gfn: 00011c00 mfn: 0011d200
(XEN) gfn: 00011e00 mfn: 00211e00
(XEN) gfn: 00012000 mfn: 0011d000
(XEN) gfn: 00012200 mfn: 00211c00
(XEN) gfn: 00012400 mfn: 0011ce00
(XEN) gfn: 00012600 mfn: 00211a00
(XEN) gfn: 00012800 mfn: 0011cc00
(XEN) gfn: 00012a00 mfn: 00211800
(XEN) gfn: 00012c00 mfn: 0011ca00
(XEN) gfn: 00012e00 mfn: 00211600
(XEN) gfn: 00013000 mfn: 0011c800
(XEN) gfn: 00013200 mfn: 00211400
(XEN) gfn: 00013400 mfn: 0011c600
(XEN) gfn: 00013600 mfn: 00211200
(XEN) gfn: 00013800 mfn: 0011c400
(XEN) gfn: 00013a00 mfn: 00211000
(XEN) gfn: 00013c00 mfn: 0011c200
(XEN) gfn: 00013e00 mfn: 00210e00
(XEN) gfn: 00014000 mfn: 0011c000
(XEN) gfn: 00014200 mfn: 00210c00
(XEN) gfn: 00014400 mfn: 0011be00
(XEN) gfn: 00014600 mfn: 00210a00
(XEN) gfn: 00014800 mfn: 0011bc00
(XEN) gfn: 00014a00 mfn: 00210800
(XEN) gfn: 00014c00 mfn: 0011ba00
(XEN) gfn: 00014e00 mfn: 00210600
(XEN) gfn: 00015000 mfn: 0011b800
(XEN) gfn: 00015200 mfn: 00210400
(XEN) gfn: 00015400 mfn: 0011b600
(XEN) gfn: 00015600 mfn: 00210200
(XEN) gfn: 00015800 mfn: 0011b400
(XEN) gfn: 00015a00 mfn: 00210000
(XEN) gfn: 00015c00 mfn: 0011b200
(XEN) gfn: 00015e00 mfn: 0020fe00
(XEN) gfn: 00016000 mfn: 0011b000
(XEN) gfn: 00016200 mfn: 0020fc00
(XEN) gfn: 00016400 mfn: 0011ae00
(XEN) gfn: 00016600 mfn: 0020fa00
(XEN) gfn: 00016800 mfn: 0011ac00
(XEN) gfn: 00016a00 mfn: 0020f800
(XEN) gfn: 00016c00 mfn: 0011aa00
(XEN) gfn: 00016e00 mfn: 0020f600
(XEN) gfn: 00017000 mfn: 0011a800
(XEN) gfn: 00017200 mfn: 0020f400
(XEN) gfn: 00017400 mfn: 0011a600
(XEN) gfn: 00017600 mfn: 0020f200
(XEN) gfn: 00017800 mfn: 0011a400
(XEN) gfn: 00017a00 mfn: 0020f000
(XEN) gfn: 00017c00 mfn: 0011a200
(XEN) gfn: 00017e00 mfn: 0020ee00
(XEN) gfn: 00018000 mfn: 0011a000
(XEN) gfn: 00018200 mfn: 0020ec00
(XEN) gfn: 00018400 mfn: 00119e00
(XEN) gfn: 00018600 mfn: 0020ea00
(XEN) gfn: 00018800 mfn: 00119c00
(XEN) gfn: 00018a00 mfn: 0020e800
(XEN) gfn: 00018c00 mfn: 00119a00
(XEN) gfn: 00018e00 mfn: 0020e600
(XEN) gfn: 00019000 mfn: 00119800
(XEN) gfn: 00019200 mfn: 0020e400
(XEN) gfn: 00019400 mfn: 00119600
(XEN) gfn: 00019600 mfn: 0020e200
(XEN) gfn: 00019800 mfn: 00119400
(XEN) gfn: 00019a00 mfn: 0020e000
(XEN) gfn: 00019c00 mfn: 00119200
(XEN) gfn: 00019e00 mfn: 0020de00
(XEN) gfn: 0001a000 mfn: 00119000
(XEN) gfn: 0001a200 mfn: 0020dc00
(XEN) gfn: 0001a400 mfn: 00118e00
(XEN) gfn: 0001a600 mfn: 0020da00
(XEN) gfn: 0001a800 mfn: 00118c00
(XEN) gfn: 0001aa00 mfn: 0020d800
(XEN) gfn: 0001ac00 mfn: 00118a00
(XEN) gfn: 0001ae00 mfn: 0020d600
(XEN) gfn: 0001b000 mfn: 00118800
(XEN) gfn: 0001b200 mfn: 0020d400
(XEN) gfn: 0001b400 mfn: 00118600
(XEN) gfn: 0001b600 mfn: 0020d200
(XEN) gfn: 0001b800 mfn: 00118400
(XEN) gfn: 0001ba00 mfn: 0020d000
(XEN) gfn: 0001bc00 mfn: 00118200
(XEN) gfn: 0001be00 mfn: 0020ce00
(XEN) gfn: 0001c000 mfn: 00118000
(XEN) gfn: 0001c200 mfn: 0020cc00
(XEN) gfn: 0001c400 mfn: 00117e00
(XEN) gfn: 0001c600 mfn: 0020ca00
(XEN) gfn: 0001c800 mfn: 00117c00
(XEN) gfn: 0001ca00 mfn: 0020c800
(XEN) gfn: 0001cc00 mfn: 00117a00
(XEN) gfn: 0001ce00 mfn: 0020c600
(XEN) gfn: 0001d000 mfn: 00117800
(XEN) gfn: 0001d200 mfn: 0020c400
(XEN) gfn: 0001d400 mfn: 00117600
(XEN) gfn: 0001d600 mfn: 0020c200
(XEN) gfn: 0001d800 mfn: 00117400
(XEN) gfn: 0001da00 mfn: 0020c000
(XEN) gfn: 0001dc00 mfn: 00117200
(XEN) gfn: 0001de00 mfn: 0020be00
(XEN) gfn: 0001e000 mfn: 00117000
(XEN) gfn: 0001e200 mfn: 0020bc00
(XEN) gfn: 0001e400 mfn: 00116e00
(XEN) gfn: 0001e600 mfn: 0020ba00
(XEN) gfn: 0001e800 mfn: 00116c00
(XEN) gfn: 0001ea00 mfn: 0020b800
(XEN) gfn: 0001ec00 mfn: 00116a00
(XEN) gfn: 0001ee00 mfn: 0020b600
(XEN) gfn: 0001f000 mfn: 00116800
(XEN) gfn: 0001f200 mfn: 0020b400
(XEN) gfn: 0001f400 mfn: 00116600
(XEN) gfn: 0001f600 mfn: 0020b200
(XEN) gfn: 0001f800 mfn: 00116400
(XEN) gfn: 0001fa00 mfn: 0020b000
(XEN) gfn: 0001fc00 mfn: 00116200
(XEN) gfn: 0001fe00 mfn: 0020ae00
(XEN) gfn: 00020000 mfn: 00116000
(XEN) gfn: 00020200 mfn: 0020ac00
(XEN) gfn: 00020400 mfn: 00115e00
(XEN) gfn: 00020600 mfn: 0020aa00
(XEN) gfn: 00020800 mfn: 00115c00
(XEN) gfn: 00020a00 mfn: 0020a800
(XEN) gfn: 00020c00 mfn: 00115a00
(XEN) gfn: 00020e00 mfn: 0020a600
(XEN) gfn: 00021000 mfn: 00115800
(XEN) gfn: 00021200 mfn: 0020a400
(XEN) gfn: 00021400 mfn: 00115600
(XEN) gfn: 00021600 mfn: 0020a200
(XEN) gfn: 00021800 mfn: 00115400
(XEN) gfn: 00021a00 mfn: 0020a000
(XEN) gfn: 00021c00 mfn: 00115200
(XEN) gfn: 00021e00 mfn: 00209e00
(XEN) gfn: 00022000 mfn: 00115000
(XEN) gfn: 00022200 mfn: 00209c00
(XEN) gfn: 00022400 mfn: 00114e00
(XEN) gfn: 00022600 mfn: 00209a00
(XEN) gfn: 00022800 mfn: 00114c00
(XEN) gfn: 00022a00 mfn: 00209800
(XEN) gfn: 00022c00 mfn: 00114a00
(XEN) gfn: 00022e00 mfn: 00209600
(XEN) gfn: 00023000 mfn: 00114800
(XEN) gfn: 00023200 mfn: 00209400
(XEN) gfn: 00023400 mfn: 00114600
(XEN) gfn: 00023600 mfn: 00209200
(XEN) gfn: 00023800 mfn: 00114400
(XEN) gfn: 00023a00 mfn: 00209000
(XEN) gfn: 00023c00 mfn: 00114200
(XEN) gfn: 00023e00 mfn: 00208e00
(XEN) gfn: 00024000 mfn: 00114000
(XEN) gfn: 00024200 mfn: 00208c00
(XEN) gfn: 00024400 mfn: 00113e00
(XEN) gfn: 00024600 mfn: 00208a00
(XEN) gfn: 00024800 mfn: 00113c00
(XEN) gfn: 00024a00 mfn: 00208800
(XEN) gfn: 00024c00 mfn: 00113a00
(XEN) gfn: 00024e00 mfn: 00208600
(XEN) gfn: 00025000 mfn: 00113800
(XEN) gfn: 00025200 mfn: 00208400
(XEN) gfn: 00025400 mfn: 00113600
(XEN) gfn: 00025600 mfn: 00208200
(XEN) gfn: 00025800 mfn: 00113400
(XEN) gfn: 00025a00 mfn: 00208000
(XEN) gfn: 00025c00 mfn: 00113200
(XEN) gfn: 00025e00 mfn: 00207e00
(XEN) gfn: 00026000 mfn: 00113000
(XEN) gfn: 00026200 mfn: 00207c00
(XEN) gfn: 00026400 mfn: 00112e00
(XEN) gfn: 00026600 mfn: 00207a00
(XEN) gfn: 00026800 mfn: 00112c00
(XEN) gfn: 00026a00 mfn: 00207800
(XEN) gfn: 00026c00 mfn: 00112a00
(XEN) gfn: 00026e00 mfn: 00207600
(XEN) gfn: 00027000 mfn: 00112800
(XEN) gfn: 00027200 mfn: 00207400
(XEN) gfn: 00027400 mfn: 00112600
(XEN) gfn: 00027600 mfn: 00207200
(XEN) gfn: 00027800 mfn: 00112400
(XEN) gfn: 00027a00 mfn: 00207000
(XEN) gfn: 00027c00 mfn: 00112200
(XEN) gfn: 00027e00 mfn: 00206e00
(XEN) gfn: 00028000 mfn: 00112000
(XEN) gfn: 00028200 mfn: 00206c00
(XEN) gfn: 00028400 mfn: 00111e00
(XEN) gfn: 00028600 mfn: 00206a00
(XEN) gfn: 00028800 mfn: 00111c00
(XEN) gfn: 00028a00 mfn: 00206800
(XEN) gfn: 00028c00 mfn: 00111a00
(XEN) gfn: 00028e00 mfn: 00206600
(XEN) gfn: 00029000 mfn: 00111800
(XEN) gfn: 00029200 mfn: 00206400
(XEN) gfn: 00029400 mfn: 00111600
(XEN) gfn: 00029600 mfn: 00206200
(XEN) gfn: 00029800 mfn: 00111400
(XEN) gfn: 00029a00 mfn: 00206000
(XEN) gfn: 00029c00 mfn: 00111200
(XEN) gfn: 00029e00 mfn: 00205e00
(XEN) gfn: 0002a000 mfn: 00111000
(XEN) gfn: 0002a200+ mfn: 00205c00
(XEN) gfn: 0002a400 mfn: 00110e00
(XEN) gfn: 0002a600 mfn: 00205a00
(XEN) gfn: 0002a800 mfn: 00110c00
(XEN) gfn: 0002aa00 mfn: 00205800
(XEN) gfn: 0002ac00 mfn: 00110a00
(XEN) gfn: 0002ae00 mfn: 00205600
(XEN) gfn: 0002b000 mfn: 00110800
(XEN) gfn: 0002b200 mfn: 00205400
(XEN) gfn: 0002b400 mfn: 00110600
(XEN) gfn: 0002b600 mfn: 00205200
(XEN) gfn: 0002b800 mfn: 00110400
(XEN) gfn: 0002ba00 mfn: 00205000
(XEN) gfn: 0002bc00 mfn: 00110200
(XEN) gfn: 0002be00 mfn: 00204e00
(XEN) gfn: 0002c000 mfn: 00110000
(XEN) gfn: 0002c200 mfn: 00204c00
(XEN) gfn: 0002c400 mfn: 0013fe00
(XEN) gfn: 0002c600 mfn: 00204a00
(XEN) gfn: 0002c800 mfn: 0013fc00
(XEN) gfn: 0002ca00 mfn: 00204800
(XEN) gfn: 0002cc00 mfn: 0013fa00
(XEN) gfn: 0002ce00 mfn: 00204600
(XEN) gfn: 0002d000 mfn: 0013f800
(XEN) gfn: 0002d200 mfn: 00204400
(XEN) gfn: 0002d400 mfn: 0013f600
(XEN) gfn: 0002d600 mfn: 00204200
(XEN) gfn: 0002d800 mfn: 0013f400
(XEN) gfn: 0002da00 mfn: 00204000
(XEN) gfn: 0002dc00 mfn: 0013f200
(XEN) gfn: 0002de00 mfn: 00203e00
(XEN) gfn: 0002e000 mfn: 0013f000
(XEN) gfn: 0002e200 mfn: 00203c00
(XEN) gfn: 0002e400 mfn: 0013ee00
(XEN) gfn: 0002e600 mfn: 00203a00
(XEN) gfn: 0002e800 mfn: 0013ec00
(XEN) gfn: 0002ea00 mfn: 00203800
(XEN) gfn: 0002ec00 mfn: 0013ea00
(XEN) gfn: 0002ee00 mfn: 00203600
(XEN) gfn: 0002f000 mfn: 0013e800
(XEN) gfn: 0002f200 mfn: 00203400
(XEN) gfn: 0002f400 mfn: 0013e600
(XEN) gfn: 0002f600 mfn: 00203200
(XEN) gfn: 0002f800 mfn: 0013e400
(XEN) gfn: 0002fa00 mfn: 00203000
(XEN) gfn: 0002fc00 mfn: 0013e200
(XEN) gfn: 0002fe00 mfn: 00202e00
(XEN) gfn: 00030000 mfn: 0013e000
(XEN) gfn: 00030200 mfn: 00202c00
(XEN) gfn: 00030400 mfn: 0013de00
(XEN) gfn: 00030600 mfn: 00202a00
(XEN) gfn: 00030800 mfn: 0013dc00
(XEN) gfn: 00030a00 mfn: 00202800
(XEN) gfn: 00030c00 mfn: 0013da00
(XEN) gfn: 00030e00 mfn: 00202600
(XEN) gfn: 00031000 mfn: 0013d800
(XEN) gfn: 00031200 mfn: 00202400
(XEN) gfn: 00031400 mfn: 0013d600
(XEN) gfn: 00031600 mfn: 00202200
(XEN) gfn: 00031800 mfn: 0013d400
(XEN) gfn: 00031a00 mfn: 00202000
(XEN) gfn: 00031c00 mfn: 0013d200
(XEN) gfn: 00031e00 mfn: 00201e00
(XEN) gfn: 00032000 mfn: 0013d000
(XEN) gfn: 00032200 mfn: 00201c00
(XEN) gfn: 00032400 mfn: 0013ce00
(XEN) gfn: 00032600 mfn: 00201a00
(XEN) gfn: 00032800 mfn: 0013cc00
(XEN) gfn: 00032a00 mfn: 00201800
(XEN) gfn: 00032c00 mfn: 0013ca00
(XEN) gfn: 00032e00 mfn: 00201600
(XEN) gfn: 00033000 mfn: 0013c800
(XEN) gfn: 00033200 mfn: 00201400
(XEN) gfn: 00033400 mfn: 0013c600
(XEN) gfn: 00033600 mfn: 00201200
(XEN) gfn: 00033800 mfn: 0013c400
(XEN) gfn: 00033a00 mfn: 00201000
(XEN) gfn: 00033c00 mfn: 0013c200
(XEN) gfn: 00033e00 mfn: 00200e00
(XEN) gfn: 00034000 mfn: 0013c000
(XEN) gfn: 00034200 mfn: 00200c00
(XEN) gfn: 00034400 mfn: 0013be00
(XEN) gfn: 00034600 mfn: 00200a00
(XEN) gfn: 00034800 mfn: 0013bc00
(XEN) gfn: 00034a00 mfn: 00200800
(XEN) gfn: 00034c00 mfn: 0013ba00
(XEN) gfn: 00034e00 mfn: 00200600
(XEN) gfn: 00035000 mfn: 0013b800
(XEN) gfn: 00035200 mfn: 00200400
(XEN) gfn: 00035400 mfn: 0013b600
(XEN) gfn: 00035600 mfn: 00200200
(XEN) gfn: 00035800 mfn: 0013b400
(XEN) gfn: 00035a00 mfn: 00200000
(XEN) gfn: 00035c00 mfn: 0013b200
(XEN) gfn: 00035e00 mfn: 0023fe00
(XEN) gfn: 00036000 mfn: 0013b000
(XEN) gfn: 00036200 mfn: 0023fc00
(XEN) gfn: 00036400 mfn: 0013ae00
(XEN) gfn: 00036600 mfn: 0023fa00
(XEN) gfn: 00036800 mfn: 0013ac00
(XEN) gfn: 00036a00 mfn: 0023f800
(XEN) gfn: 00036c00 mfn: 0013aa00
(XEN) gfn: 00036e00 mfn: 0023f600
(XEN) gfn: 00037000 mfn: 0013a800
(XEN) gfn: 00037200 mfn: 0023f400
(XEN) gfn: 00037400 mfn: 0013a600
(XEN) gfn: 00037600 mfn: 0023f200
(XEN) gfn: 00037800 mfn: 0013a400
(XEN) gfn: 00037a00 mfn: 0023f000
(XEN) gfn: 00037c00 mfn: 0013a200
(XEN) gfn: 00037e00 mfn: 0023ee00
(XEN) gfn: 00038000 mfn: 0013a000
(XEN) gfn: 00038200 mfn: 0023ec00
(XEN) gfn: 00038400 mfn: 00139e00
(XEN) gfn: 00038600 mfn: 0023ea00
(XEN) gfn: 00038800 mfn: 00139c00
(XEN) gfn: 00038a00 mfn: 0023e800
(XEN) gfn: 00038c00 mfn: 00139a00
(XEN) gfn: 00038e00 mfn: 0023e600
(XEN) gfn: 00039000 mfn: 00139800
(XEN) gfn: 00039200 mfn: 0023e400
(XEN) gfn: 00039400 mfn: 00139600
(XEN) gfn: 00039600 mfn: 0023e200
(XEN) gfn: 00039800 mfn: 00139400
(XEN) gfn: 00039a00 mfn: 0023e000
(XEN) gfn: 00039c00 mfn: 00139200
(XEN) gfn: 00039e00 mfn: 0023de00
(XEN) gfn: 0003a000 mfn: 00139000
(XEN) gfn: 0003a200 mfn: 0023dc00
(XEN) gfn: 0003a400 mfn: 00138e00
(XEN) gfn: 0003a600 mfn: 0023da00
(XEN) gfn: 0003a800 mfn: 00138c00
(XEN) gfn: 0003aa00 mfn: 0023d800
(XEN) gfn: 0003ac00 mfn: 00138a00
(XEN) gfn: 0003ae00 mfn: 0023d600
(XEN) gfn: 0003b000 mfn: 00138800
(XEN) gfn: 0003b200 mfn: 0023d400
(XEN) gfn: 0003b400 mfn: 00138600
(XEN) gfn: 0003b600 mfn: 0023d200
(XEN) gfn: 0003b800 mfn: 00138400
(XEN) gfn: 0003ba00 mfn: 0023d000
(XEN) gfn: 0003bc00 mfn: 00138200
(XEN) gfn: 0003be00 mfn: 0023ce00
(XEN) gfn: 0003c000 mfn: 00138000
(XEN) gfn: 0003c200 mfn: 0023cc00
(XEN) gfn: 0003c400 mfn: 00137e00
(XEN) gfn: 0003c600 mfn: 0023ca00
(XEN) gfn: 0003c800 mfn: 00137c00
(XEN) gfn: 0003ca00 mfn: 0023c800
(XEN) gfn: 0003cc00 mfn: 00137a00
(XEN) gfn: 0003ce00 mfn: 0023c600
(XEN) gfn: 0003d000 mfn: 00137800
(XEN) gfn: 0003d200 mfn: 0023c400
(XEN) gfn: 0003d400 mfn: 00137600
(XEN) gfn: 0003d600 mfn: 0023c200
(XEN) gfn: 0003d800 mfn: 00137400
(XEN) gfn: 0003da00 mfn: 0023c000
(XEN) gfn: 0003dc00 mfn: 00137200
(XEN) gfn: 0003de00 mfn: 0023be00
(XEN) gfn: 0003e000 mfn: 00137000
(XEN) gfn: 0003e200 mfn: 0023bc00
(XEN) gfn: 0003e400 mfn: 00136e00
(XEN) gfn: 0003e600 mfn: 0023ba00
(XEN) gfn: 0003e800 mfn: 00136c00
(XEN) gfn: 0003ea00 mfn: 0023b800
(XEN) gfn: 0003ec00 mfn: 00136a00
(XEN) gfn: 0003ee00 mfn: 0023b600
(XEN) gfn: 0003f000 mfn: 00136800
(XEN) gfn: 0003f200 mfn: 0023b400
(XEN) gfn: 0003f400 mfn: 00136600
(XEN) gfn: 0003f600 mfn: 0023b200
(XEN) gfn: 0003f800 mfn: 00136400
(XEN) gfn: 0003fa00 mfn: 0023b000
(XEN) gfn: 0003fc00 mfn: 00136200
(XEN) gfn: 0003fe00 mfn: 0023ae00
(XEN) gfn: 00040000 mfn: 00040000
(XEN) gfn: 00080000 mfn: 0023ac00
(XEN) gfn: 00080200 mfn: 00136000
(XEN) gfn: 00080400 mfn: 0023aa00
(XEN) gfn: 00080600 mfn: 00135e00
(XEN) gfn: 00080800 mfn: 0023a800
(XEN) gfn: 00080a00 mfn: 00135c00
(XEN) gfn: 00080c00 mfn: 0023a600
(XEN) gfn: 00080e00 mfn: 00135a00
(XEN) gfn: 00081000 mfn: 0023a400
(XEN) gfn: 00081200 mfn: 00135800
(XEN) gfn: 00081400 mfn: 0023a200
(XEN) gfn: 00081600 mfn: 00135600
(XEN) gfn: 00081800 mfn: 0023a000
(XEN) gfn: 00081a00 mfn: 00135400
(XEN) gfn: 00081c00 mfn: 00239e00
(XEN) gfn: 00081e00 mfn: 00135200
(XEN) gfn: 00082000 mfn: 00239c00
(XEN) gfn: 00082200 mfn: 00135000
(XEN) gfn: 00082400 mfn: 00239a00
(XEN) gfn: 00082600 mfn: 00134e00
(XEN) gfn: 00082800 mfn: 00239800
(XEN) gfn: 00082a00 mfn: 00134c00
(XEN) gfn: 00082c00 mfn: 00239600
(XEN) gfn: 00082e00 mfn: 00134a00
(XEN) gfn: 00083000 mfn: 00239400
(XEN) gfn: 00083200 mfn: 00134800
(XEN) gfn: 00083400 mfn: 00239200
(XEN) gfn: 00083600 mfn: 00134600
(XEN) gfn: 00083800 mfn: 00239000
(XEN) gfn: 00083a00 mfn: 00134400
(XEN) gfn: 00083c00 mfn: 00238e00
(XEN) gfn: 00083e00 mfn: 00134200
(XEN) gfn: 00084000 mfn: 00238c00
(XEN) gfn: 00084200 mfn: 00134000
(XEN) gfn: 00084400 mfn: 00238a00
(XEN) gfn: 00084600 mfn: 00133e00
(XEN) gfn: 00084800 mfn: 00238800
(XEN) gfn: 00084a00 mfn: 00133c00
(XEN) gfn: 00084c00 mfn: 00238600
(XEN) gfn: 00084e00 mfn: 00133a00
(XEN) gfn: 00085000 mfn: 00238400
(XEN) gfn: 00085200 mfn: 00133800
(XEN) gfn: 00085400 mfn: 00238200
(XEN) gfn: 00085600 mfn: 00133600
(XEN) gfn: 00085800 mfn: 00238000
(XEN) gfn: 00085a00 mfn: 00133400
(XEN) gfn: 00085c00 mfn: 00237e00
(XEN) gfn: 00085e00 mfn: 00133200
(XEN) gfn: 00086000 mfn: 00237c00
(XEN) gfn: 00086200 mfn: 00133000
(XEN) gfn: 00086400 mfn: 00237a00
(XEN) gfn: 00086600 mfn: 00132e00
(XEN) gfn: 00086800 mfn: 00237800
(XEN) gfn: 00086a00 mfn: 00132c00
(XEN) gfn: 00086c00 mfn: 00237600
(XEN) gfn: 00086e00 mfn: 00132a00
(XEN) gfn: 00087000 mfn: 00237400
(XEN) gfn: 00087200 mfn: 00132800
(XEN) gfn: 00087400 mfn: 00237200
(XEN) gfn: 00087600 mfn: 00132600
(XEN) gfn: 00087800 mfn: 00237000
(XEN) gfn: 00087a00 mfn: 00132400
(XEN) gfn: 00087c00 mfn: 00236e00
(XEN) gfn: 00087e00 mfn: 00132200
(XEN) gfn: 00088000 mfn: 00236c00
(XEN) gfn: 00088200 mfn: 00132000
(XEN) gfn: 00088400 mfn: 00236a00
(XEN) gfn: 00088600 mfn: 00131e00
(XEN) gfn: 00088800 mfn: 00236800
(XEN) gfn: 00088a00 mfn: 00131c00
(XEN) gfn: 00088c00 mfn: 00236600
(XEN) gfn: 00088e00 mfn: 00131a00
(XEN) gfn: 00089000 mfn: 00236400
(XEN) gfn: 00089200 mfn: 00131800
(XEN) gfn: 00089400 mfn: 00236200
(XEN) gfn: 00089600 mfn: 00131600
(XEN) gfn: 00089800 mfn: 00236000
(XEN) gfn: 00089a00 mfn: 00131400
(XEN) gfn: 00089c00 mfn: 00235e00
(XEN) gfn: 00089e00 mfn: 00131200
(XEN) gfn: 0008a000 mfn: 00235c00
(XEN) gfn: 0008a200 mfn: 00131000
(XEN) gfn: 0008a400 mfn: 00235a00
(XEN) gfn: 0008a600 mfn: 00130e00
(XEN) gfn: 0008a800 mfn: 00235800
(XEN) gfn: 0008aa00 mfn: 00130c00
(XEN) gfn: 0008ac00 mfn: 00235600
(XEN) gfn: 0008ae00 mfn: 00130a00
(XEN) gfn: 0008b000 mfn: 00235400
(XEN) gfn: 0008b200 mfn: 00130800
(XEN) gfn: 0008b400 mfn: 00235200
(XEN) gfn: 0008b600 mfn: 00130600
(XEN) gfn: 0008b800 mfn: 00235000
(XEN) gfn: 0008ba00 mfn: 00130400
(XEN) gfn: 0008bc00 mfn: 00234e00
(XEN) gfn: 0008be00 mfn: 00130200
(XEN) gfn: 0008c000 mfn: 00234c00
(XEN) gfn: 0008c200 mfn: 00130000
(XEN) gfn: 0008c400 mfn: 00234a00
(XEN) gfn: 0008c600 mfn: 0012fe00
(XEN) gfn: 0008c800 mfn: 00234800
(XEN) gfn: 0008ca00 mfn: 0012fc00
(XEN) gfn: 0008cc00 mfn: 00234600
(XEN) gfn: 0008ce00 mfn: 0012fa00
(XEN) gfn: 0008d000 mfn: 00234400
(XEN) gfn: 0008d200 mfn: 0012f800
(XEN) gfn: 0008d400 mfn: 00234200
(XEN) gfn: 0008d600 mfn: 0012f600
(XEN) gfn: 0008d800 mfn: 00234000
(XEN) gfn: 0008da00 mfn: 0012f400
(XEN) gfn: 0008dc00 mfn: 00233e00
(XEN) gfn: 0008de00 mfn: 0012f200
(XEN) gfn: 0008e000 mfn: 00233c00
(XEN) gfn: 0008e200 mfn: 0012f000
(XEN) gfn: 0008e400 mfn: 00233a00
(XEN) gfn: 0008e600 mfn: 0012ee00
(XEN) gfn: 0008e800 mfn: 00233800
(XEN) gfn: 0008ea00 mfn: 0012ec00
(XEN) gfn: 0008ec00 mfn: 00233600
(XEN) gfn: 0008ee00 mfn: 0012ea00
(XEN) gfn: 0008f000 mfn: 00233400
(XEN) gfn: 0008f200 mfn: 0012e800
(XEN) gfn: 0008f400 mfn: 00233200
(XEN) gfn: 0008f600 mfn: 0012e600
(XEN) gfn: 0008f800 mfn: 00233000
(XEN) gfn: 0008fa00 mfn: 0012e400
(XEN) gfn: 0008fc00 mfn: 00232e00
(XEN) gfn: 0008fe00 mfn: 0012e200
(XEN) gfn: 00090000 mfn: 00232c00
(XEN) gfn: 00090200 mfn: 0012e000
(XEN) gfn: 00090400 mfn: 00232a00
(XEN) gfn: 00090600 mfn: 0012de00
(XEN) gfn: 00090800 mfn: 00232800
(XEN) gfn: 00090a00 mfn: 0012dc00
(XEN) gfn: 00090c00 mfn: 00232600
(XEN) gfn: 00090e00 mfn: 0012da00
(XEN) gfn: 00091000 mfn: 00232400
(XEN) gfn: 00091200 mfn: 0012d800
(XEN) gfn: 00091400 mfn: 00232200
(XEN) gfn: 00091600 mfn: 0012d600
(XEN) gfn: 00091800 mfn: 00232000
(XEN) gfn: 00091a00 mfn: 0012d400
(XEN) gfn: 00091c00 mfn: 00231e00
(XEN) gfn: 00091e00 mfn: 0012d200
(XEN) gfn: 00092000 mfn: 00231c00
(XEN) gfn: 00092200 mfn: 0012d000
(XEN) gfn: 00092400 mfn: 00231a00
(XEN) gfn: 00092600 mfn: 0012ce00
(XEN) gfn: 00092800 mfn: 00231800
(XEN) gfn: 00092a00 mfn: 0012cc00
(XEN) gfn: 00092c00 mfn: 00231600
(XEN) gfn: 00092e00 mfn: 0012ca00
(XEN) gfn: 00093000 mfn: 00231400
(XEN) gfn: 00093200 mfn: 0012c800
(XEN) gfn: 00093400 mfn: 00231200
(XEN) gfn: 00093600 mfn: 0012c600
(XEN) gfn: 00093800 mfn: 00231000
(XEN) gfn: 00093a00 mfn: 0012c400
(XEN) gfn: 00093c00 mfn: 00230e00
(XEN) gfn: 00093e00 mfn: 0012c200
(XEN) gfn: 00094000 mfn: 00230c00
(XEN) gfn: 00094200 mfn: 0012c000
(XEN) gfn: 00094400 mfn: 00230a00
(XEN) gfn: 00094600 mfn: 0012be00
(XEN) gfn: 00094800 mfn: 00230800
(XEN) gfn: 00094a00 mfn: 0012bc00
(XEN) gfn: 00094c00 mfn: 00230600
(XEN) gfn: 00094e00 mfn: 0012ba00
(XEN) gfn: 00095000 mfn: 00230400
(XEN) gfn: 00095200 mfn: 0012b800
(XEN) gfn: 00095400 mfn: 00230200
(XEN) gfn: 00095600 mfn: 0012b600
(XEN) gfn: 00095800 mfn: 00230000
(XEN) gfn: 00095a00 mfn: 0012b400
(XEN) gfn: 00095c00 mfn: 0022fe00
(XEN) gfn: 00095e00 mfn: 0012b200
(XEN) gfn: 00096000 mfn: 0022fc00
(XEN) gfn: 00096200 mfn: 0012b000
(XEN) gfn: 00096400 mfn: 0022fa00
(XEN) gfn: 00096600 mfn: 0012ae00
(XEN) gfn: 00096800 mfn: 0022f800
(XEN) gfn: 00096a00 mfn: 0012ac00
(XEN) gfn: 00096c00 mfn: 0022f600
(XEN) gfn: 00096e00 mfn: 0012aa00
(XEN) gfn: 00097000 mfn: 0022f400
(XEN) gfn: 00097200 mfn: 0012a800
(XEN) gfn: 00097400 mfn: 0022f200
(XEN) gfn: 00097600 mfn: 0012a600
(XEN) gfn: 00097800 mfn: 0022f000
(XEN) gfn: 00097a00 mfn: 0012a400
(XEN) gfn: 00097c00 mfn: 0022ee00
(XEN) gfn: 00097e00 mfn: 0012a200
(XEN) gfn: 00098000 mfn: 0022ec00
(XEN) gfn: 00098200 mfn: 0012a000
(XEN) gfn: 00098400 mfn: 0022ea00
(XEN) gfn: 00098600 mfn: 00129e00
(XEN) gfn: 00098800 mfn: 0022e800
(XEN) gfn: 00098a00 mfn: 00129c00
(XEN) gfn: 00098c00 mfn: 0022e600
(XEN) gfn: 00098e00 mfn: 00129a00
(XEN) gfn: 00099000 mfn: 0022e400
(XEN) gfn: 00099200 mfn: 00129800
(XEN) gfn: 00099400 mfn: 0022e200
(XEN) gfn: 00099600 mfn: 00129600
(XEN) gfn: 00099800 mfn: 0022e000
(XEN) gfn: 00099a00 mfn: 00129400
(XEN) gfn: 00099c00 mfn: 0022de00
(XEN) gfn: 00099e00 mfn: 00129200
(XEN) gfn: 0009a000 mfn: 0022dc00
(XEN) gfn: 0009a200 mfn: 00129000
(XEN) gfn: 0009a400 mfn: 0022da00
(XEN) gfn: 0009a600 mfn: 00128e00
(XEN) gfn: 0009a800 mfn: 0022d800
(XEN) gfn: 0009aa00 mfn: 00128c00
(XEN) gfn: 0009ac00 mfn: 0022d600
(XEN) gfn: 0009ae00 mfn: 00128a00
(XEN) gfn: 0009b000 mfn: 0022d400
(XEN) gfn: 0009b200 mfn: 00128800
(XEN) gfn: 0009b400 mfn: 0022d200
(XEN) gfn: 0009b600 mfn: 00128600
(XEN) gfn: 0009b800 mfn: 0022d000
(XEN) gfn: 0009ba00 mfn: 00128400
(XEN) gfn: 0009bc00 mfn: 0022ce00
(XEN) gfn: 0009be00 mfn: 00128200
(XEN) gfn: 0009c000 mfn: 0022cc00
(XEN) gfn: 0009c200 mfn: 00128000
(XEN) gfn: 0009c400 mfn: 0022ca00
(XEN) gfn: 0009c600 mfn: 00127e00
(XEN) gfn: 0009c800 mfn: 0022c800
(XEN) gfn: 0009ca00 mfn: 00127c00
(XEN) gfn: 0009cc00 mfn: 0022c600
(XEN) gfn: 0009ce00 mfn: 00127a00
(XEN) gfn: 0009d000 mfn: 0022c400
(XEN) gfn: 0009d200 mfn: 00127800
(XEN) gfn: 0009d400 mfn: 0022c200
(XEN) gfn: 0009d600 mfn: 00127600
(XEN) gfn: 0009d800 mfn: 0022c000
(XEN) gfn: 0009da00 mfn: 00127400
(XEN) gfn: 0009dc00 mfn: 0022be00
(XEN) gfn: 0009de00 mfn: 00127200
(XEN) gfn: 0009e000 mfn: 0022bc00
(XEN) gfn: 0009e200 mfn: 00127000
(XEN) gfn: 0009e400 mfn: 0022ba00
(XEN) gfn: 0009e600 mfn: 00126e00
(XEN) gfn: 0009e800 mfn: 0022b800
(XEN) gfn: 0009ea00 mfn: 00126c00
(XEN) gfn: 0009ec00 mfn: 0022b600
(XEN) gfn: 0009ee00 mfn: 00126a00
(XEN) gfn: 0009f000 mfn: 0022b400
(XEN) gfn: 0009f200 mfn: 00126800
(XEN) gfn: 0009f400 mfn: 0022b200
(XEN) gfn: 0009f600 mfn: 00126600
(XEN) gfn: 0009f800 mfn: 0022b000
(XEN) gfn: 0009fa00 mfn: 00126400
(XEN) gfn: 0009fc00 mfn: 0022ae00
(XEN) gfn: 0009fe00 mfn: 00126200
(XEN) gfn: 000a0000 mfn: 0022ac00
(XEN) gfn: 000a0200 mfn: 00126000
(XEN) gfn: 000a0400 mfn: 0022aa00
(XEN) gfn: 000a0600 mfn: 00125e00
(XEN) gfn: 000a0800 mfn: 0022a800
(XEN) gfn: 000a0a00 mfn: 00125c00
(XEN) gfn: 000a0c00 mfn: 0022a600
(XEN) gfn: 000a0e00 mfn: 00125a00
(XEN) gfn: 000a1000 mfn: 0022a400
(XEN) gfn: 000a1200 mfn: 00125800
(XEN) gfn: 000a1400 mfn: 0022a200
(XEN) gfn: 000a1600 mfn: 00125600
(XEN) gfn: 000a1800 mfn: 0022a000
(XEN) gfn: 000a1a00 mfn: 00125400
(XEN) gfn: 000a1c00 mfn: 00229e00
(XEN) gfn: 000a1e00 mfn: 00125200
(XEN) gfn: 000a2000 mfn: 00229c00
(XEN) gfn: 000a2200 mfn: 00125000
(XEN) gfn: 000a2400 mfn: 00229a00
(XEN) gfn: 000a2600 mfn: 00124e00
(XEN) gfn: 000a2800 mfn: 00229800
(XEN) gfn: 000a2a00 mfn: 00124c00
(XEN) gfn: 000a2c00 mfn: 00229600
(XEN) gfn: 000a2e00 mf+n: 00124a00
(XEN) gfn: 000a3000 mfn: 00229400
(XEN) gfn: 000a3200 mfn: 00124800
(XEN) gfn: 000a3400 mfn: 00229200
(XEN) gfn: 000a3600 mfn: 00124600
(XEN) gfn: 000a3800 mfn: 00229000
(XEN) gfn: 000a3a00 mfn: 00124400
(XEN) gfn: 000a3c00 mfn: 00228e00
(XEN) gfn: 000a3e00 mfn: 00124200
(XEN) gfn: 000a4000 mfn: 00228c00
(XEN) gfn: 000a4200 mfn: 00124000
(XEN) gfn: 000a4400 mfn: 00228a00
(XEN) gfn: 000a4600 mfn: 00123e00
(XEN) gfn: 000a4800 mfn: 00228800
(XEN) gfn: 000a4a00 mfn: 00123c00
(XEN) gfn: 000a4c00 mfn: 00228600
(XEN) gfn: 000a4e00 mfn: 00123a00
(XEN) gfn: 000a5000 mfn: 00228400
(XEN) gfn: 000a5200 mfn: 00123800
(XEN) gfn: 000a5400 mfn: 00228200
(XEN) gfn: 000a5600 mfn: 00123600
(XEN) gfn: 000a5800 mfn: 00228000
(XEN) gfn: 000a5a00 mfn: 00123400
(XEN) gfn: 000a5c00 mfn: 00227e00
(XEN) gfn: 000a5e00 mfn: 00123200
(XEN) gfn: 000a6000 mfn: 00227c00
(XEN) gfn: 000a6200 mfn: 00123000
(XEN) gfn: 000a6400 mfn: 00227a00
(XEN) gfn: 000a6600 mfn: 00122e00
(XEN) gfn: 000a6800 mfn: 00227800
(XEN) gfn: 000a6a00 mfn: 00122c00
(XEN) gfn: 000a6c00 mfn: 00227600
(XEN) gfn: 000a6e00 mfn: 00122a00
(XEN) gfn: 000a7000 mfn: 00227400
(XEN) gfn: 000a7200 mfn: 00122800
(XEN) gfn: 000a7400 mfn: 00227200
(XEN) gfn: 000a7600 mfn: 00122600
(XEN) gfn: 000a7800 mfn: 00227000
(XEN) gfn: 000a7a00 mfn: 00122400
(XEN) gfn: 000a7c00 mfn: 00226e00
(XEN) gfn: 000a7e00 mfn: 00122200
(XEN) gfn: 000a8000 mfn: 00226c00
(XEN) gfn: 000a8200 mfn: 00122000
(XEN) gfn: 000a8400 mfn: 00226a00
(XEN) gfn: 000a8600 mfn: 00121e00
(XEN) gfn: 000a8800 mfn: 00226800
(XEN) gfn: 000a8a00 mfn: 00121c00
(XEN) gfn: 000a8c00 mfn: 00226600
(XEN) gfn: 000a8e00 mfn: 00121a00
(XEN) gfn: 000a9000 mfn: 00226400
(XEN) gfn: 000a9200 mfn: 00121800
(XEN) gfn: 000a9400 mfn: 00226200
(XEN) gfn: 000a9600 mfn: 00121600
(XEN) gfn: 000a9800 mfn: 00226000
(XEN) gfn: 000a9a00 mfn: 00121400
(XEN) gfn: 000a9c00 mfn: 00225e00
(XEN) gfn: 000a9e00 mfn: 00121200
(XEN) gfn: 000aa000 mfn: 00225c00
(XEN) gfn: 000aa200 mfn: 00121000
(XEN) gfn: 000aa400 mfn: 00225a00
(XEN) gfn: 000aa600 mfn: 00120e00
(XEN) gfn: 000aa800 mfn: 00225800
(XEN) gfn: 000aaa00 mfn: 00120c00
(XEN) gfn: 000aac00 mfn: 00225600
(XEN) gfn: 000aae00 mfn: 00120a00
(XEN) gfn: 000ab000 mfn: 00225400
(XEN) gfn: 000ab200 mfn: 00120800
(XEN) gfn: 000ab400 mfn: 00225200
(XEN) gfn: 000ab600 mfn: 00120600
(XEN) gfn: 000ab800 mfn: 00225000
(XEN) gfn: 000aba00 mfn: 00120400
(XEN) gfn: 000abc00 mfn: 00224e00
(XEN) gfn: 000abe00 mfn: 00120200
(XEN) gfn: 000ac000 mfn: 00224c00
(XEN) gfn: 000ac200 mfn: 00120000
(XEN) gfn: 000ac400 mfn: 00224a00
(XEN) gfn: 000ac600 mfn: 00080800
(XEN) gfn: 000ac800 mfn: 00224800
(XEN) gfn: 000aca00 mfn: 00081000
(XEN) gfn: 000acc00 mfn: 00224600
(XEN) gfn: 000ace00 mfn: 00081600
(XEN) gfn: 000ad000 mfn: 00224400
(XEN) gfn: 000ad200 mfn: 00081400
(XEN) gfn: 000ad400 mfn: 00224200
(XEN) gfn: 000ad600 mfn: 00080600
(XEN) gfn: 000ad800 mfn: 00224000
(XEN) gfn: 000ada00 mfn: 00080400
(XEN) gfn: 000adc00 mfn: 00223e00
(XEN) gfn: 000ade00 mfn: 00080200
(XEN) gfn: 000ae000 mfn: 00223c00
(XEN) gfn: 000ae200 mfn: 00080000
(XEN) gfn: 000ae400 mfn: 00223a00
(XEN) gfn: 000ae600 mfn: 00081e00
(XEN) gfn: 000ae800 mfn: 00223800
(XEN) gfn: 000aea00 mfn: 00081c00
(XEN) gfn: 000aec00 mfn: 00223600
(XEN) gfn: 000aee00 mfn: 00081a00
(XEN) gfn: 000af000 mfn: 00223400
(XEN) gfn: 000af200 mfn: 00081800
(XEN) gfn: 000af400 mfn: 00223200
(XEN) gfn: 000af600 mfn: 00083e00
(XEN) gfn: 000af800 mfn: 00223000
(XEN) gfn: 000afa00 mfn: 00083c00
(XEN) gfn: 000afc00 mfn: 00222e00
(XEN) gfn: 000afe00 mfn: 00083a00
(XEN) gfn: 000b0000 mfn: 00222c00
(XEN) gfn: 000b0200 mfn: 00083800
(XEN) gfn: 000b0400 mfn: 00222a00
(XEN) gfn: 000b0600 mfn: 00083600
(XEN) gfn: 000b0800 mfn: 00222800
(XEN) gfn: 000b0a00 mfn: 00083400
(XEN) gfn: 000b0c00 mfn: 00222600
(XEN) gfn: 000b0e00 mfn: 00083200
(XEN) gfn: 000b1000 mfn: 00222400
(XEN) gfn: 000b1200 mfn: 00083000
(XEN) gfn: 000b1400 mfn: 00222200
(XEN) gfn: 000b1600 mfn: 00082e00
(XEN) gfn: 000b1800 mfn: 00222000
(XEN) gfn: 000b1a00 mfn: 00082c00
(XEN) gfn: 000b1c00 mfn: 00221e00
(XEN) gfn: 000b1e00 mfn: 00082a00
(XEN) gfn: 000b2000 mfn: 00221c00
(XEN) gfn: 000b2200 mfn: 00082800
(XEN) gfn: 000b2400 mfn: 00221a00
(XEN) gfn: 000b2600 mfn: 00082600
(XEN) gfn: 000b2800 mfn: 00221800
(XEN) gfn: 000b2a00 mfn: 00082400
(XEN) gfn: 000b2c00 mfn: 00221600
(XEN) gfn: 000b2e00 mfn: 00082200
(XEN) gfn: 000b3000 mfn: 00221400
(XEN) gfn: 000b3200 mfn: 00082000
(XEN) gfn: 000b3400 mfn: 00221200
(XEN) gfn: 000b3600 mfn: 00087e00
(XEN) gfn: 000b3800 mfn: 00221000
(XEN) gfn: 000b3a00 mfn: 00087c00
(XEN) gfn: 000b3c00 mfn: 00220e00
(XEN) gfn: 000b3e00 mfn: 00087a00
(XEN) gfn: 000b4000 mfn: 00220c00
(XEN) gfn: 000b4200 mfn: 00087800
(XEN) gfn: 000b4400 mfn: 00220a00
(XEN) gfn: 000b4600 mfn: 00087600
(XEN) gfn: 000b4800 mfn: 00220800
(XEN) gfn: 000b4a00 mfn: 00087400
(XEN) gfn: 000b4c00 mfn: 00220600
(XEN) gfn: 000b4e00 mfn: 00087200
(XEN) gfn: 000b5000 mfn: 00220400
(XEN) gfn: 000b5200 mfn: 00087000
(XEN) gfn: 000b5400 mfn: 00220200
(XEN) gfn: 000b5600 mfn: 00086e00
(XEN) gfn: 000b5800 mfn: 00220000
(XEN) gfn: 000b5a00 mfn: 00086c00
(XEN) gfn: 000b5c00 mfn: 001c0800
(XEN) gfn: 000b5e00 mfn: 00086a00
(XEN) gfn: 000b6000 mfn: 001b0400
(XEN) gfn: 000b6200 mfn: 00086800
(XEN) gfn: 000b6400 mfn: 00162c00
(XEN) gfn: 000b6600 mfn: 00086600
(XEN) gfn: 000b6800 mfn: 001d0e00
(XEN) gfn: 000b6a00 mfn: 00086400
(XEN) gfn: 000b6c00 mfn: 001d0c00
(XEN) gfn: 000b6e00 mfn: 00086200
(XEN) gfn: 000b7000 mfn: 001b1a00
(XEN) gfn: 000b7200 mfn: 00086000
(XEN) gfn: 000b7400 mfn: 001b1800
(XEN) gfn: 000b7600 mfn: 00085e00
(XEN) gfn: 000b7800 mfn: 001b0e00
(XEN) gfn: 000b7a00 mfn: 00085c00
(XEN) gfn: 000b7c00 mfn: 001b0c00
(XEN) gfn: 000b7e00 mfn: 00085a00
(XEN) gfn: 000b8000 mfn: 001b0200
(XEN) gfn: 000b8200 mfn: 00085800
(XEN) gfn: 000b8400 mfn: 001b0000
(XEN) gfn: 000b8600 mfn: 00085600
(XEN) gfn: 000b8800 mfn: 00162a00
(XEN) gfn: 000b8a00 mfn: 00085400
(XEN) gfn: 000b8c00 mfn: 00162800
(XEN) gfn: 000b8e00 mfn: 00085200
(XEN) gfn: 000b9000 mfn: 001c0600
(XEN) gfn: 000b9200 mfn: 00085000
(XEN) gfn: 000b9400 mfn: 001c0400
(XEN) gfn: 000b9600 mfn: 00084e00
(XEN) gfn: 000b9800 mfn: 001c0200
(XEN) gfn: 000b9a00 mfn: 00084c00
(XEN) gfn: 000b9c00 mfn: 001c0000
(XEN) gfn: 000b9e00 mfn: 00084a00
(XEN) gfn: 000ba000 mfn: 001b1600
(XEN) gfn: 000ba200 mfn: 00084800
(XEN) gfn: 000ba400 mfn: 001b1400
(XEN) gfn: 000ba600 mfn: 00084600
(XEN) gfn: 000ba800 mfn: 001b1200
(XEN) gfn: 000baa00 mfn: 00084400
(XEN) gfn: 000bac00 mfn: 001b1000
(XEN) gfn: 000bae00 mfn: 00084200
(XEN) gfn: 000bb000 mfn: 00162600
(XEN) gfn: 000bb200 mfn: 00084000
(XEN) gfn: 000bb400 mfn: 00162400
(XEN) gfn: 000bb600 mfn: 0008fe00
(XEN) gfn: 000bb800 mfn: 00162200
(XEN) gfn: 000bba00 mfn: 0008fc00
(XEN) gfn: 000bbc00 mfn: 00162000
(XEN) gfn: 000bbe00 mfn: 0008fa00
(XEN) gfn: 000bc000 mfn: 001d1e00
(XEN) gfn: 000bc200 mfn: 0008f800
(XEN) gfn: 000bc400 mfn: 001d1c00
(XEN) gfn: 000bc600 mfn: 0008f600
(XEN) gfn: 000bc800 mfn: 001d1a00
(XEN) gfn: 000bca00 mfn: 0008f400
(XEN) gfn: 000bcc00 mfn: 001d1800
(XEN) gfn: 000bce00 mfn: 0008f200
(XEN) gfn: 000bd000 mfn: 001d1600
(XEN) gfn: 000bd200 mfn: 0008f000
(XEN) gfn: 000bd400 mfn: 001d1400
(XEN) gfn: 000bd600 mfn: 0008ee00
(XEN) gfn: 000bd800 mfn: 001d1200
(XEN) gfn: 000bda00 mfn: 0008ec00
(XEN) gfn: 000bdc00 mfn: 001d1000
(XEN) gfn: 000bde00 mfn: 0008ea00
(XEN) gfn: 000be000 mfn: 001d3e00
(XEN) gfn: 000be200 mfn: 0008e800
(XEN) gfn: 000be400 mfn: 001d3c00
(XEN) gfn: 000be600 mfn: 0008e600
(XEN) gfn: 000be800 mfn: 001d3a00
(XEN) gfn: 000bea00 mfn: 0008e400
(XEN) gfn: 000bec00 mfn: 001d3800
(XEN) gfn: 000bee00 mfn: 0008e200
(XEN) gfn: 000bf000 mfn: 001d3600
(XEN) gfn: 000bf200 mfn: 0008e000
(XEN) gfn: 000bf400 mfn: 001d3400
(XEN) gfn: 000bf600 mfn: 0008de00
(XEN) gfn: 000bf800 mfn: 001d3200
(XEN) gfn: 000bfa00 mfn: 0008dc00
(XEN) gfn: 000bfc00 mfn: 001d3000
(XEN) gfn: 000bfe00 mfn: 0008da00
(XEN) gfn: 000c0000 mfn: 001d2e00
(XEN) gfn: 000c0200 mfn: 0008d800
(XEN) gfn: 000c0400 mfn: 001d2c00
(XEN) gfn: 000c0600 mfn: 0008d600
(XEN) gfn: 000c0800 mfn: 001d2a00
(XEN) gfn: 000c0a00 mfn: 0008d400
(XEN) gfn: 000c0c00 mfn: 001d2800
(XEN) gfn: 000c0e00 mfn: 0008d200
(XEN) gfn: 000c1000 mfn: 001d2600
(XEN) gfn: 000c1200 mfn: 0008d000
(XEN) gfn: 000c1400 mfn: 001d2400
(XEN) gfn: 000c1600 mfn: 0008ce00
(XEN) gfn: 000c1800 mfn: 001d2200
(XEN) gfn: 000c1a00 mfn: 0008cc00
(XEN) gfn: 000c1c00 mfn: 001d2000
(XEN) gfn: 000c1e00 mfn: 0008ca00
(XEN) gfn: 000c2000 mfn: 001b3e00
(XEN) gfn: 000c2200 mfn: 0008c800
(XEN) gfn: 000c2400 mfn: 001b3c00
(XEN) gfn: 000c2600 mfn: 0008c600
(XEN) gfn: 000c2800 mfn: 001b3a00
(XEN) gfn: 000c2a00 mfn: 0008c400
(XEN) gfn: 000c2c00 mfn: 001b3800
(XEN) gfn: 000c2e00 mfn: 0008c200
(XEN) gfn: 000c3000 mfn: 001b3600
(XEN) gfn: 000c3200 mfn: 0008c000
(XEN) gfn: 000c3400 mfn: 001b3400
(XEN) gfn: 000c3600 mfn: 0008be00
(XEN) gfn: 000c3800 mfn: 001b3200
(XEN) gfn: 000c3a00 mfn: 0008bc00
(XEN) gfn: 000c3c00 mfn: 001b3000
(XEN) gfn: 000c3e00 mfn: 0008ba00
(XEN) gfn: 000c4000 mfn: 001b2e00
(XEN) gfn: 000c4200 mfn: 0008b800
(XEN) gfn: 000c4400 mfn: 001b2c00
(XEN) gfn: 000c4600 mfn: 0008b600
(XEN) gfn: 000c4800 mfn: 001b2a00
(XEN) gfn: 000c4a00 mfn: 0008b400
(XEN) gfn: 000c4c00 mfn: 001b2800
(XEN) gfn: 000c4e00 mfn: 0008b200
(XEN) gfn: 000c5000 mfn: 001b2600
(XEN) gfn: 000c5200 mfn: 0008b000
(XEN) gfn: 000c5400 mfn: 001b2400
(XEN) gfn: 000c5600 mfn: 0008ae00
(XEN) gfn: 000c5800 mfn: 001b2200
(XEN) gfn: 000c5a00 mfn: 0008ac00
(XEN) gfn: 000c5c00 mfn: 001b2000
(XEN) gfn: 000c5e00 mfn: 0008aa00
(XEN) gfn: 000c6000 mfn: 00161e00
(XEN) gfn: 000c6200 mfn: 0008a800
(XEN) gfn: 000c6400 mfn: 00161c00
(XEN) gfn: 000c6600 mfn: 0008a600
(XEN) gfn: 000c6800 mfn: 00161a00
(XEN) gfn: 000c6a00 mfn: 0008a400
(XEN) gfn: 000c6c00 mfn: 00161800
(XEN) gfn: 000c6e00 mfn: 0008a200
(XEN) gfn: 000c7000 mfn: 00161600
(XEN) gfn: 000c7200 mfn: 0008a000
(XEN) gfn: 000c7400 mfn: 00161400
(XEN) gfn: 000c7600 mfn: 00089e00
(XEN) gfn: 000c7800 mfn: 00161200
(XEN) gfn: 000c7a00 mfn: 00089c00
(XEN) gfn: 000c7c00 mfn: 00161000
(XEN) gfn: 000c7e00 mfn: 00089a00
(XEN) gfn: 000c8000 mfn: 00160e00
(XEN) gfn: 000c8200 mfn: 00089800
(XEN) gfn: 000c8400 mfn: 00160c00
(XEN) gfn: 000c8600 mfn: 00089600
(XEN) gfn: 000c8800 mfn: 00160a00
(XEN) gfn: 000c8a00 mfn: 00089400
(XEN) gfn: 000c8c00 mfn: 00160800
(XEN) gfn: 000c8e00 mfn: 00089200
(XEN) gfn: 000c9000 mfn: 00160600
(XEN) gfn: 000c9200 mfn: 00089000
(XEN) gfn: 000c9400 mfn: 00160400
(XEN) gfn: 000c9600 mfn: 00088e00
(XEN) gfn: 000c9800 mfn: 00160200
(XEN) gfn: 000c9a00 mfn: 00088c00
(XEN) gfn: 000c9c00 mfn: 00160000
(XEN) gfn: 000c9e00 mfn: 00088a00
(XEN) gfn: 000ca000 mfn: 001d7e00
(XEN) gfn: 000ca200 mfn: 00088800
(XEN) gfn: 000ca400 mfn: 001d7c00
(XEN) gfn: 000ca600 mfn: 00088600
(XEN) gfn: 000ca800 mfn: 001d7a00
(XEN) gfn: 000caa00 mfn: 00088400
(XEN) gfn: 000cac00 mfn: 001d7800
(XEN) gfn: 000cae00 mfn: 00088200
(XEN) gfn: 000cb000 mfn: 001d7600
(XEN) gfn: 000cb200 mfn: 00088000
(XEN) gfn: 000cb400 mfn: 001d7400
(XEN) gfn: 000cb600 mfn: 0009fe00
(XEN) gfn: 000cb800 mfn: 001d7200
(XEN) gfn: 000cba00 mfn: 0009fc00
(XEN) gfn: 000cbc00 mfn: 001d7000
(XEN) gfn: 000cbe00 mfn: 0009fa00
(XEN) gfn: 000cc000 mfn: 001d6e00
(XEN) gfn: 000cc200 mfn: 0009f800
(XEN) gfn: 000cc400 mfn: 001d6c00
(XEN) gfn: 000cc600 mfn: 0009f600
(XEN) gfn: 000cc800 mfn: 001d6a00
(XEN) gfn: 000cca00 mfn: 0009f400
(XEN) gfn: 000ccc00 mfn: 001d6800
(XEN) gfn: 000cce00 mfn: 0009f200
(XEN) gfn: 000cd000 mfn: 001d6600
(XEN) gfn: 000cd200 mfn: 0009f000
(XEN) gfn: 000cd400 mfn: 001d6400
(XEN) gfn: 000cd600 mfn: 0009ee00
(XEN) gfn: 000cd800 mfn: 001d6200
(XEN) gfn: 000cda00 mfn: 0009ec00
(XEN) gfn: 000cdc00 mfn: 001d6000
(XEN) gfn: 000cde00 mfn: 0009ea00
(XEN) gfn: 000ce000 mfn: 001d5e00
(XEN) gfn: 000ce200 mfn: 0009e800
(XEN) gfn: 000ce400 mfn: 001d5c00
(XEN) gfn: 000ce600 mfn: 0009e600
(XEN) gfn: 000ce800 mfn: 001d5a00
(XEN) gfn: 000cea00 mfn: 0009e400
(XEN) gfn: 000cec00 mfn: 001d5800
(XEN) gfn: 000cee00 mfn: 0009e200
(XEN) gfn: 000cf000 mfn: 001d5600
(XEN) gfn: 000cf200 mfn: 0009e000
(XEN) gfn: 000cf400 mfn: 001d5400
(XEN) gfn: 000cf600 mfn: 0009de00
(XEN) gfn: 000cf800 mfn: 001d5200
(XEN) gfn: 000cfa00 mfn: 0009dc00
(XEN) gfn: 000cfc00 mfn: 001d5000
(XEN) gfn: 000cfe00 mfn: 0009da00
(XEN) gfn: 000d0000 mfn: 001d4e00
(XEN) gfn: 000d0200 mfn: 0009d800
(XEN) gfn: 000d0400 mfn: 001d4c00
(XEN) gfn: 000d0600 mfn: 0009d600
(XEN) gfn: 000d0800 mfn: 001d4a00
(XEN) gfn: 000d0a00 mfn: 0009d400
(XEN) gfn: 000d0c00 mfn: 001d4800
(XEN) gfn: 000d0e00 mfn: 0009d200
(XEN) gfn: 000d1000 mfn: 001d4600
(XEN) gfn: 000d1200 mfn: 0009d000
(XEN) gfn: 000d1400 mfn: 001d4400
(XEN) gfn: 000d1600 mfn: 0009ce00
(XEN) gfn: 000d1800 mfn: 001d4200
(XEN) gfn: 000d1a00 mfn: 0009cc00
(XEN) gfn: 000d1c00 mfn: 001d4000
(XEN) gfn: 000d1e00 mfn: 0009ca00
(XEN) gfn: 000d2000 mfn: 001b7e00
(XEN) gfn: 000d2200 mfn: 0009c800
(XEN) gfn: 000d2400 mfn: 001b7c00
(XEN) gfn: 000d2600 mfn: 0009c600
(XEN) gfn: 000d2800 mfn: 001b7a00
(XEN) gfn: 000d2a00 mfn: 0009c400
(XEN) gfn: 000d2c00 mfn: 001b7800
(XEN) gfn: 000d2e00 mfn: 0009c200
(XEN) gfn: 000d3000 mfn: 001b7600
(XEN) gfn: 000d3200 mfn: 0009c000
(XEN) gfn: 000d3400 mfn: 001b7400
(XEN) gfn: 000d3600 mfn: 0009be00
(XEN) gfn: 000d3800 mfn: 001b7200
(XEN) gfn: 000d3a00 mfn: 0009bc00
(XEN) gfn: 000d3c00 mfn: 001b7000
(XEN) gfn: 000d3e00 mfn: 0009ba00
(XEN) gfn: 000d4000 mfn: 001b6e00
(XEN) gfn: 000d4200 mfn: 0009b800
(XEN) gfn: 000d4400 mfn: 001b6c00
(XEN) gfn: 000d4600 mfn: 0009b600
(XEN) gfn: 000d4800 mfn: 001b6a00
(XEN) gfn: 000d4a00 mfn: 0009b400
(XEN) gfn: 000d4c00 mfn: 001b6800
(XEN) gfn: 000d4e00 mfn: 0009b200
(XEN) gfn: 000d5000 mfn: 001b6600
(XEN) gfn: 000d5200 mfn: 0009b000
(XEN) gfn: 000d5400 mfn: 001b6400
(XEN) gfn: 000d5600 mfn: 0009ae00
(XEN) gfn: 000d5800 mfn: 001b6200
(XEN) gfn: 000d5a00 mfn: 0009ac00
(XEN) gfn: 000d5c00 mfn: 001b6000
(XEN) gfn: 000d5e00 mfn: 0009aa00
(XEN) gfn: 000d6000 mfn: 001b5e00
(XEN) gfn: 000d6200 mfn: 0009a800
(XEN) gfn: 000d6400 mfn: 001b5c00
(XEN) gfn: 000d6600 mfn: 0009a600
(XEN) gfn: 000d6800 mfn: 001b5a00
(XEN) gfn: 000d6a00 mfn: 0009a400
(XEN) gfn: 000d6c00 mfn: 001b5800
(XEN) gfn: 000d6e00 mfn: 0009a200
(XEN) gfn: 000d7000 mfn: 001b5600
(XEN) gfn: 000d7200 mfn: 0009a000
(XEN) gfn: 000d7400 mfn: 001b5400
(XEN) gfn: 000d7600 mfn: 00099e00
(XEN) gfn: 000d7800 mfn: 001b5200
(XEN) gfn: 000d7a00 mfn: 00099c00
(XEN) gfn: 000d7c00 mfn: 001b5000
(XEN) gfn: 000d7e00 mfn: 00099a00
(XEN) gfn: 000d8000 mfn: 001b4e00
(XEN) gfn: 000d8200 mfn: 00099800
(XEN) gfn: 000d8400 mfn: 001b4c00
(XEN) gfn: 000d8600 mfn: 00099600
(XEN) gfn: 000d8800 mfn: 001b4a00
(XEN) gfn: 000d8a00 mfn: 00099400
(XEN) gfn: 000d8c00 mfn: 001b4800
(XEN) gfn: 000d8e00 mfn: 00099200
(XEN) gfn: 000d9000 mfn: 001b4600
(XEN) gfn: 000d9200 mfn: 00099000
(XEN) gfn: 000d9400 mfn: 001b4400
(XEN) gfn: 000d9600 mfn: 00098e00
(XEN) gfn: 000d9800 mfn: 001b4200
(XEN) gfn: 000d9a00 mfn: 00098c00
(XEN) gfn: 000d9c00 mfn: 001b4000
(XEN) gfn: 000d9e00 mfn: 00098a00
(XEN) gfn: 000da000 mfn: 001dfe00
(XEN) gfn: 000da200 mfn: 00098800
(XEN) gfn: 000da400 mfn: 001dfc00
(XEN) gfn: 000da600 mfn: 00098600
(XEN) gfn: 000da800 mfn: 001dfa00
(XEN) gfn: 000daa00 mfn: 00098400
(XEN) gfn: 000dac00 mfn: 001df800
(XEN) gfn: 000dae00 mfn: 00098200
(XEN) gfn: 000db000 mfn: 001df600
(XEN) gfn: 000db200 mfn: 00098000
(XEN) gfn: 000db400 mfn: 001df400
(XEN) gfn: 000db600 mfn: 00097e00
(XEN) gfn: 000db800 mfn: 001df200
(XEN) gfn: 000dba00 mfn: 00097c00
(XEN) gfn: 000dbc00 mfn: 0+01df000
(XEN) gfn: 000dbe00 mfn: 00097a00
(XEN) gfn: 000dc000 mfn: 001dee00
(XEN) gfn: 000dc200 mfn: 00097800
(XEN) stdvga.c:151:d2 leaving stdvga
(XEN) gfn: 000dc400 mfn: 001dec00
(XEN) gfn: 000dc600 mfn: 00097600
(XEN) gfn: 000dc800 mfn: 001dea00
(XEN) gfn: 000dca00 mfn: 00097400
(XEN) gfn: 000dcc00 mfn: 001de800
(XEN) gfn: 000dce00 mfn: 00097200
(XEN) gfn: 000dd000 mfn: 001de600
(XEN) gfn: 000dd200 mfn: 00097000
(XEN) gfn: 000dd400 mfn: 001de400
(XEN) gfn: 000dd600 mfn: 00096e00
(XEN) gfn: 000dd800 mfn: 001de200
(XEN) gfn: 000dda00 mfn: 00096c00
(XEN) gfn: 000ddc00 mfn: 001de000
(XEN) gfn: 000dde00 mfn: 00096a00
(XEN) gfn: 000de000 mfn: 001dde00
(XEN) gfn: 000de200 mfn: 00096800
(XEN) gfn: 000de400 mfn: 001ddc00
(XEN) gfn: 000de600 mfn: 00096600
(XEN) gfn: 000de800 mfn: 001dda00
(XEN) gfn: 000dea00 mfn: 00096400
(XEN) gfn: 000dec00 mfn: 001dd800
(XEN) gfn: 000dee00 mfn: 00096200
(XEN) gfn: 000df000 mfn: 001dd600
(XEN) gfn: 000df200 mfn: 00096000
(XEN) gfn: 000df400 mfn: 001dd400
(XEN) gfn: 000df600 mfn: 00095e00
(XEN) gfn: 000df800 mfn: 001dd200
(XEN) gfn: 000dfa00 mfn: 00095c00
(XEN) gfn: 000dfc00 mfn: 001dd000
(XEN) gfn: 000dfe00 mfn: 00095a00
(XEN) gfn: 000e0000 mfn: 001dce00
(XEN) gfn: 000e0200 mfn: 00095800
(XEN) gfn: 000e0400 mfn: 001dcc00
(XEN) gfn: 000e0600 mfn: 00095600
(XEN) gfn: 000e0800 mfn: 001dca00
(XEN) gfn: 000e0a00 mfn: 00095400
(XEN) gfn: 000e0c00 mfn: 001dc800
(XEN) gfn: 000e0e00 mfn: 00095200
(XEN) gfn: 000e1000 mfn: 001dc600
(XEN) gfn: 000e1200 mfn: 00095000
(XEN) gfn: 000e1400 mfn: 001dc400
(XEN) gfn: 000e1600 mfn: 00094e00
(XEN) gfn: 000e1800 mfn: 001dc200
(XEN) gfn: 000e1a00 mfn: 00094c00
(XEN) gfn: 000e1c00 mfn: 001dc000
(XEN) gfn: 000e1e00 mfn: 00094a00
(XEN) gfn: 000e2000 mfn: 001dbe00
(XEN) gfn: 000e2200 mfn: 00094800
(XEN) gfn: 000e2400 mfn: 001dbc00
(XEN) gfn: 000e2600 mfn: 00094600
(XEN) gfn: 000e2800 mfn: 001dba00
(XEN) gfn: 000e2a00 mfn: 00094400
(XEN) gfn: 000e2c00 mfn: 001db800
(XEN) gfn: 000e2e00 mfn: 00094200
(XEN) gfn: 000e3000 mfn: 001db600
(XEN) gfn: 000e3200 mfn: 00094000
(XEN) gfn: 000e3400 mfn: 001db400
(XEN) gfn: 000e3600 mfn: 00093e00
(XEN) gfn: 000e3800 mfn: 001db200
(XEN) gfn: 000e3a00 mfn: 00093c00
(XEN) gfn: 000e3c00 mfn: 001db000
(XEN) gfn: 000e3e00 mfn: 00093a00
(XEN) gfn: 000e4000 mfn: 001dae00
(XEN) gfn: 000e4200 mfn: 00093800
(XEN) gfn: 000e4400 mfn: 001dac00
(XEN) gfn: 000e4600 mfn: 00093600
(XEN) gfn: 000e4800 mfn: 001daa00
(XEN) gfn: 000e4a00 mfn: 00093400
(XEN) gfn: 000e4c00 mfn: 001da800
(XEN) gfn: 000e4e00 mfn: 00093200
(XEN) gfn: 000e5000 mfn: 001da600
(XEN) gfn: 000e5200 mfn: 00093000
(XEN) gfn: 000e5400 mfn: 001da400
(XEN) gfn: 000e5600 mfn: 00092e00
(XEN) gfn: 000e5800 mfn: 001da200
(XEN) gfn: 000e5a00 mfn: 00092c00
(XEN) gfn: 000e5c00 mfn: 001da000
(XEN) gfn: 000e5e00 mfn: 00092a00
(XEN) gfn: 000e6000 mfn: 001d9e00
(XEN) gfn: 000e6200 mfn: 00092800
(XEN) gfn: 000e6400 mfn: 001d9c00
(XEN) gfn: 000e6600 mfn: 00092600
(XEN) gfn: 000e6800 mfn: 001d9a00
(XEN) gfn: 000e6a00 mfn: 00092400
(XEN) gfn: 000e6c00 mfn: 001d9800
(XEN) gfn: 000e6e00 mfn: 00092200
(XEN) gfn: 000e7000 mfn: 001d9600
(XEN) gfn: 000e7200 mfn: 00092000
(XEN) gfn: 000e7400 mfn: 001d9400
(XEN) gfn: 000e7600 mfn: 00091e00
(XEN) gfn: 000e7800 mfn: 001d9200
(XEN) gfn: 000e7a00 mfn: 00091c00
(XEN) gfn: 000e7c00 mfn: 001d9000
(XEN) gfn: 000e7e00 mfn: 00091a00
(XEN) gfn: 000e8000 mfn: 001d8e00
(XEN) gfn: 000e8200 mfn: 00091800
(XEN) gfn: 000e8400 mfn: 001d8c00
(XEN) gfn: 000e8600 mfn: 00091600
(XEN) gfn: 000e8800 mfn: 001d8a00
(XEN) gfn: 000e8a00 mfn: 00091400
(XEN) gfn: 000e8c00 mfn: 001d8800
(XEN) gfn: 000e8e00 mfn: 00091200
(XEN) gfn: 000e9000 mfn: 001d8600
(XEN) gfn: 000e9200 mfn: 00091000
(XEN) gfn: 000e9400 mfn: 001d8400
(XEN) gfn: 000e9600 mfn: 00090e00
(XEN) gfn: 000e9800 mfn: 001d8200
(XEN) gfn: 000e9a00 mfn: 00090c00
(XEN) gfn: 000e9c00 mfn: 001d8000
(XEN) gfn: 000e9e00 mfn: 00090a00
(XEN) gfn: 000ea000 mfn: 001bfe00
(XEN) gfn: 000ea200 mfn: 00090800
(XEN) gfn: 000ea400 mfn: 001bfc00
(XEN) gfn: 000ea600 mfn: 00090600
(XEN) gfn: 000ea800 mfn: 001bfa00
(XEN) gfn: 000eaa00 mfn: 00090400
(XEN) gfn: 000eac00 mfn: 001bf800
(XEN) gfn: 000eae00 mfn: 00090200
(XEN) gfn: 000eb000 mfn: 001bf600
(XEN) gfn: 000eb200 mfn: 00090000
(XEN) gfn: 000eb400 mfn: 001bf400
(XEN) gfn: 000eb600 mfn: 001bf200
(XEN) gfn: 000eb800 mfn: 001bf000
(XEN) gfn: 000eba00 mfn: 001bee00
(XEN) gfn: 000ebc00 mfn: 001bec00
(XEN) gfn: 000ebe00 mfn: 001bea00
(XEN) gfn: 000ec000 mfn: 001be800
(XEN) gfn: 000ec200 mfn: 001be600
(XEN) gfn: 000ec400 mfn: 001be400
(XEN) gfn: 000ec600 mfn: 001be200
(XEN) gfn: 000ec800 mfn: 001be000
(XEN) gfn: 000eca00 mfn: 001bde00
(XEN) gfn: 000ecc00 mfn: 001bdc00
(XEN) gfn: 000ece00 mfn: 001bda00
(XEN) gfn: 000ed000 mfn: 001bd800
(XEN) gfn: 000ed200 mfn: 001bd600
(XEN) gfn: 000ed400 mfn: 001bd400
(XEN) gfn: 000ed600 mfn: 001bd200
(XEN) gfn: 000ed800 mfn: 001bd000
(XEN) gfn: 000eda00 mfn: 001bce00
(XEN) gfn: 000edc00 mfn: 001bcc00
(XEN) gfn: 000ede00 mfn: 001bca00
(XEN) gfn: 000ee000 mfn: 001bc800
(XEN) gfn: 000ee200 mfn: 001bc600
(XEN) gfn: 000ee400 mfn: 001bc400
(XEN) gfn: 000ee600 mfn: 001bc200
(XEN) gfn: 000ee800 mfn: 001bc000
(XEN) gfn: 000eea00 mfn: 001bbe00
(XEN) gfn: 000eec00 mfn: 001bbc00
(XEN) gfn: 000eee00 mfn: 001bba00
(XEN) gfn: 000ef000 mfn: 001bb800
(XEN) gfn: 000ef200 mfn: 001bb600
(XEN) gfn: 000ef400 mfn: 001bb400
(XEN) gfn: 000ef600 mfn: 001bb200
(XEN) gfn: 000ef800 mfn: 001bb000
(XEN) gfn: 000efa00 mfn: 001bae00
(XEN) gfn: 000efc00 mfn: 001bac00
(XEN) gfn: 000efe00 mfn: 001baa00
(XEN) gfn: 000f0000 mfn: 00218e0e
(XEN) gfn: 000f0001 mfn: 00101e2a
(XEN) gfn: 000f0002 mfn: 00218e0d
(XEN) gfn: 000f0003 mfn: 0010288f
(XEN) gfn: 000f0004 mfn: 00218e0c
(XEN) gfn: 000f0005 mfn: 0010288e
(XEN) gfn: 000f0006 mfn: 00218e0b
(XEN) gfn: 000f0007 mfn: 0010153b
(XEN) gfn: 000f0008 mfn: 00218e0a
(XEN) gfn: 000f0009 mfn: 0010153a
(XEN) gfn: 000f000a mfn: 00218e09
(XEN) gfn: 000f000b mfn: 00102857
(XEN) gfn: 000f000c mfn: 00218e08
(XEN) gfn: 000f000d mfn: 00102856
(XEN) gfn: 000f000e mfn: 00218e07
(XEN) gfn: 000f000f mfn: 001015b7
(XEN) gfn: 000f0010 mfn: 00218e06
(XEN) gfn: 000f0011 mfn: 001015b6
(XEN) gfn: 000f0012 mfn: 00218e05
(XEN) gfn: 000f0013 mfn: 00102827
(XEN) gfn: 000f0014 mfn: 00218e04
(XEN) gfn: 000f0015 mfn: 00102826
(XEN) gfn: 000f0016 mfn: 00218e03
(XEN) gfn: 000f0017 mfn: 0010052b
(XEN) gfn: 000f0018 mfn: 00218e02
(XEN) gfn: 000f0019 mfn: 0010052a
(XEN) gfn: 000f001a mfn: 00218e01
(XEN) gfn: 000f001b mfn: 00102817
(XEN) gfn: 000f001c mfn: 00218e00
(XEN) gfn: 000f001d mfn: 00102816
(XEN) gfn: 000f001e mfn: 001b1c4a
(XEN) gfn: 000f001f mfn: 00102c3b
(XEN) gfn: 000f0020 mfn: 001b1f9a
(XEN) gfn: 000f0021 mfn: 00102c3a
(XEN) gfn: 000f0022 mfn: 001d0b12
(XEN) gfn: 000f0023 mfn: 00102c8b
(XEN) gfn: 000f0024 mfn: 001d0b0b
(XEN) gfn: 000f0025 mfn: 00102c8a
(XEN) gfn: 000f0026 mfn: 001d0b8d
(XEN) gfn: 000f0027 mfn: 0010270f
(XEN) gfn: 000f0028 mfn: 001b1fc3
(XEN) gfn: 000f0029 mfn: 0010270e
(XEN) gfn: 000f002a mfn: 001b1c23
(XEN) gfn: 000f002b mfn: 00101ebb
(XEN) gfn: 000f002c mfn: 001d0bb8
(XEN) gfn: 000f002d mfn: 00101eba
(XEN) gfn: 000f002e mfn: 001d0bbc
(XEN) gfn: 000f002f mfn: 00102e6b
(XEN) gfn: 000f0030 mfn: 001d0b9c
(XEN) gfn: 000f0031 mfn: 00102e6a
(XEN) gfn: 000f0032 mfn: 001d0bc6
(XEN) gfn: 000f0033 mfn: 00102c5f
(XEN) gfn: 000f0034 mfn: 001d0b46
(XEN) gfn: 000f0035 mfn: 00102c5e
(XEN) gfn: 000f0036 mfn: 001d0b44
(XEN) gfn: 000f0037 mfn: 00102e93
(XEN) gfn: 000f0038 mfn: 001d0bad
(XEN) gfn: 000f0039 mfn: 00102e92
(XEN) gfn: 000f003a mfn: 001d0bae
(XEN) gfn: 000f003b mfn: 0010289b
(XEN) gfn: 000f003c mfn: 001d0b41
(XEN) gfn: 000f003d mfn: 0010289a
(XEN) gfn: 000f003e mfn: 001b1fea
(XEN) gfn: 000f003f mfn: 00102cc7
(XEN) gfn: 000f0040 mfn: 001d0bc1
(XEN) gfn: 000f0041 mfn: 00102cc6
(XEN) gfn: 000f0042 mfn: 001b1fdf
(XEN) gfn: 000f0043 mfn: 00102963
(XEN) gfn: 000f0044 mfn: 001d0b37
(XEN) gfn: 000f0045 mfn: 00102962
(XEN) gfn: 000f0046 mfn: 001d0b9e
(XEN) gfn: 000f0047 mfn: 00102887
(XEN) gfn: 000f0048 mfn: 001b06d8
(XEN) gfn: 000f0049 mfn: 00102886
(XEN) gfn: 000f004a mfn: 00162ed8
(XEN) gfn: 000f004b mfn: 001019c5
(XEN) gfn: 000f004c mfn: 001632d8
(XEN) gfn: 000f004d mfn: 001019c4
(XEN) gfn: 000f004e mfn: 001c0a61
(XEN) gfn: 000f004f mfn: 001019c3
(XEN) gfn: 000f0050 mfn: 001c0a60
(XEN) gfn: 000f0051 mfn: 001019c2
(XEN) gfn: 000f0052 mfn: 001b1c49
(XEN) gfn: 000f0053 mfn: 0010150f
(XEN) gfn: 000f0054 mfn: 001b1c48
(XEN) gfn: 000f0055 mfn: 0010150e
(XEN) gfn: 000f0056 mfn: 001b1f99
(XEN) gfn: 000f0057 mfn: 00101aa9
(XEN) gfn: 000f0058 mfn: 001b1f98
(XEN) gfn: 000f0059 mfn: 00101aa8
(XEN) gfn: 000f005a mfn: 001d0b65
(XEN) gfn: 000f005b mfn: 00101aa7
(XEN) gfn: 000f005c mfn: 001d0b64
(XEN) gfn: 000f005d mfn: 00101aa6
(XEN) gfn: 000f005e mfn: 001d0b11
(XEN) gfn: 000f005f mfn: 00101985
(XEN) gfn: 000f0060 mfn: 001d0b10
(XEN) gfn: 000f0061 mfn: 00101984
(XEN) gfn: 000f0062 mfn: 001d0bc5
(XEN) gfn: 000f0063 mfn: 00101983
(XEN) gfn: 000f0064 mfn: 001d0bc4
(XEN) gfn: 000f0065 mfn: 00101982
(XEN) gfn: 000f0066 mfn: 001d0b43
(XEN) gfn: 000f0067 mfn: 00101e6b
(XEN) gfn: 000f0068 mfn: 001d0b42
(XEN) gfn: 000f0069 mfn: 00101e6a
(XEN) gfn: 000f006a mfn: 001b1fe9
(XEN) gfn: 000f006b mfn: 00102763
(XEN) gfn: 000f006c mfn: 001b1fe8
(XEN) gfn: 000f006d mfn: 00102762
(XEN) gfn: 000f006e mfn: 001d0bc3
(XEN) gfn: 000f006f mfn: 00102d3f
(XEN) gfn: 000f0070 mfn: 001d0bc2
(XEN) gfn: 000f0071 mfn: 00102d3e
(XEN) gfn: 000f0072 mfn: 001d0bff
(XEN) gfn: 000f0073 mfn: 0010046b
(XEN) gfn: 000f0074 mfn: 001d0bfe
(XEN) gfn: 000f0075 mfn: 0010046a
(XEN) gfn: 000f0076 mfn: 001d0bfd
(XEN) gfn: 000f0077 mfn: 001003d7
(XEN) gfn: 000f0078 mfn: 001d0bfc
(XEN) gfn: 000f0079 mfn: 001003d6
(XEN) gfn: 000f007a mfn: 001d0bcf
(XEN) gfn: 000f007b mfn: 0010031b
(XEN) gfn: 000f007c mfn: 001d0bce
(XEN) gfn: 000f007d mfn: 0010031a
(XEN) gfn: 000f007e mfn: 001d0bcd
(XEN) gfn: 000f007f mfn: 00102dc7
(XEN) gfn: 000f0080 mfn: 001d0bcc
(XEN) gfn: 000f0081 mfn: 00102dc6
(XEN) gfn: 000f0082 mfn: 001d0b0f
(XEN) gfn: 000f0083 mfn: 00101d97
(XEN) gfn: 000f0084 mfn: 001d0b0e
(XEN) gfn: 000f0085 mfn: 00101d96
(XEN) gfn: 000f0086 mfn: 001d0b0d
(XEN) gfn: 000f0087 mfn: 0010276b
(XEN) gfn: 000f0088 mfn: 001d0b0c
(XEN) gfn: 000f0089 mfn: 0010276a
(XEN) gfn: 000f008a mfn: 001630bf
(XEN) gfn: 000f008b mfn: 00101a33
(XEN) gfn: 000f008c mfn: 001630be
(XEN) gfn: 000f008d mfn: 00101a32
(XEN) gfn: 000f008e mfn: 001630bd
(XEN) gfn: 000f008f mfn: 0010253d
(XEN) gfn: 000f0090 mfn: 001630bc
(XEN) gfn: 000f0091 mfn: 0010253c
(XEN) gfn: 000f0092 mfn: 001b1c47
(XEN) gfn: 000f0093 mfn: 00102369
(XEN) gfn: 000f0094 mfn: 001b1c46
(XEN) gfn: 000f0095 mfn: 00102368
(XEN) gfn: 000f0096 mfn: 001b1c45
(XEN) gfn: 000f0097 mfn: 0010283f
(XEN) gfn: 000f0098 mfn: 001b1c44
(XEN) gfn: 000f0099 mfn: 0010283e
(XEN) gfn: 000f009a mfn: 001b1c43
(XEN) gfn: 000f009b mfn: 00101583
(XEN) gfn: 000f009c mfn: 001b1c42
(XEN) gfn: 000f009d mfn: 00101582
(XEN) gfn: 000f009e mfn: 001b1c41
(XEN) gfn: 000f009f mfn: 0010180b
(XEN) gfn: 000f00a0 mfn: 001b1c40
(XEN) gfn: 000f00a1 mfn: 0010180a
(XEN) gfn: 000f00a2 mfn: 001b1f97
(XEN) gfn: 000f00a3 mfn: 0010294f
(XEN) gfn: 000f00a4 mfn: 001b1f96
(XEN) gfn: 000f00a5 mfn: 0010294e
(XEN) gfn: 000f00a6 mfn: 001b1f95
(XEN) gfn: 000f00a7 mfn: 00102d1f
(XEN) gfn: 000f00a8 mfn: 001b1f94
(XEN) gfn: 000f00a9 mfn: 00102d1e
(XEN) gfn: 000f00aa mfn: 001b1f93
(XEN) gfn: 000f00ab mfn: 00102379
(XEN) gfn: 000f00ac mfn: 001b1f92
(XEN) gfn: 000f00ad mfn: 00102378
(XEN) gfn: 000f00ae mfn: 001b1f91
(XEN) gfn: 000f00af mfn: 00102ca3
(XEN) gfn: 000f00b0 mfn: 001b1f90
(XEN) gfn: 000f00b1 mfn: 00102ca2
(XEN) gfn: 000f00b2 mfn: 001b06d7
(XEN) gfn: 000f00b3 mfn: 0010282f
(XEN) gfn: 000f00b4 mfn: 001b06d6
(XEN) gfn: 000f00b5 mfn: 0010282e
(XEN) gfn: 000f00b6 mfn: 001b06d5
(XEN) gfn: 000f00b7 mfn: 00102e5f
(XEN) gfn: 000f00b8 mfn: 001b06d4
(XEN) gfn: 000f00b9 mfn: 00102e5e
(XEN) gfn: 000f00ba mfn: 001b06d3
(XEN) gfn: 000f00bb mfn: 00102777
(XEN) gfn: 000f00bc mfn: 001b06d2
(XEN) gfn: 000f00bd mfn: 00102776
(XEN) gfn: 000f00be mfn: 001b06d1
(XEN) gfn: 000f00bf mfn: 001019f7
(XEN) gfn: 000f00c0 mfn: 001b06d0
(XEN) gfn: 000f00c1 mfn: 001019f6
(XEN) gfn: 000f00c2 mfn: 00162ed7
(XEN) gfn: 000f00c3 mfn: 00101a93
(XEN) gfn: 000f00c4 mfn: 00162ed6
(XEN) gfn: 000f00c5 mfn: 00101a92
(XEN) gfn: 000f00c6 mfn: 00162ed5
(XEN) gfn: 000f00c7 mfn: 0010141f
(XEN) gfn: 000f00c8 mfn: 00162ed4
(XEN) gfn: 000f00c9 mfn: 0010141e
(XEN) gfn: 000f00ca mfn: 00162ed3
(XEN) gfn: 000f00cb mfn: 0010140b
(XEN) gfn: 000f00cc mfn: 00162ed2
(XEN) gfn: 000f00cd mfn: 0010140a
(XEN) gfn: 000f00ce mfn: 00162ed1
(XEN) gfn: 000f00cf mfn: 00102c67
(XEN) gfn: 000f00d0 mfn: 00162ed0
(XEN) gfn: 000f00d1 mfn: 00102c66
(XEN) gfn: 000f00d2 mfn: 001632d7
(XEN) gfn: 000f00d3 mfn: 00102517
(XEN) gfn: 000f00d4 mfn: 001632d6
(XEN) gfn: 000f00d5 mfn: 00102516
(XEN) gfn: 000f00d6 mfn: 001632d5
(XEN) gfn: 000f00d7 mfn: 0010274f
(XEN) gfn: 000f00d8 mfn: 001632d4
(XEN) gfn: 000f00d9 mfn: 0010274e
(XEN) gfn: 000f00da mfn: 001632d3
(XEN) gfn: 000f00db mfn: 00102a27
(XEN) gfn: 000f00dc mfn: 001632d2
(XEN) gfn: 000f00dd mfn: 00102a26
(XEN) gfn: 000f00de mfn: 001632d1
(XEN) gfn: 000f00df mfn: 00102eb7
(XEN) gfn: 000f00e0 mfn: 001632d0
(XEN) gfn: 000f00e1 mfn: 00102eb6
(XEN) gfn: 000f00e2 mfn: 001d0bdf
(XEN) gfn: 000f00e3 mfn: 00102943
(XEN) gfn: 000f00e4 mfn: 001d0bde
(XEN) gfn: 000f00e5 mfn: 00102942
(XEN) gfn: 000f00e6 mfn: 001d0bdd
(XEN) gfn: 000f00e7 mfn: 0010271f
(XEN) gfn: 000f00e8 mfn: 001d0bdc
(XEN) gfn: 000f00e9 mfn: 0010271e
(XEN) gfn: 000f00ea mfn: 001d0bdb
(XEN) gfn: 000f00eb mfn: 00102837
(XEN) gfn: 000f00ec mfn: 001d0bda
(XEN) gfn: 000f00ed mfn: 00102836
(XEN) gfn: 000f00ee mfn: 001d0bd9
(XEN) gfn: 000f00ef mfn: 00102da3
(XEN) gfn: 000f00f0 mfn: 001d0bd8
(XEN) gfn: 000f00f1 mfn: 00102da2
(XEN) gfn: 000f00f2 mfn: 001d0bd7
(XEN) gfn: 000f00f3 mfn: 00101927
(XEN) gfn: 000f00f4 mfn: 001d0bd6
(XEN) gfn: 000f00f5 mfn: 00101926
(XEN) gfn: 000f00f6 mfn: 001d0bd5
(XEN) gfn: 000f00f7 mfn: 00102dab
(XEN) gfn: 000f00f8 mfn: 001d0bd4
(XEN) gfn: 000f00f9 mfn: 00102daa
(XEN) gfn: 000f00fa mfn: 001d0bd3
(XEN) gfn: 000f00fb mfn: 00102e1b
(XEN) gfn: 000f00fc mfn: 001d0bd2
(XEN) gfn: 000f00fd mfn: 00102e1a
(XEN) gfn: 000f00fe mfn: 001d0bd1
(XEN) gfn: 000f00ff mfn: 00101943
(XEN) gfn: 000f0100 mfn: 001d0bd0
(XEN) gfn: 000f0101 mfn: 00101942
(XEN) gfn: 000f0102 mfn: 001b1f8f
(XEN) gfn: 000f0103 mfn: 00102bef
(XEN) gfn: 000f0104 mfn: 001b1f8e
(XEN) gfn: 000f0105 mfn: 00102bee
(XEN) gfn: 000f0106 mfn: 001b1f8d
(XEN) gfn: 000f0107 mfn: 00101def
(XEN) gfn: 000f0108 mfn: 001b1f8c
(XEN) gfn: 000f0109 mfn: 00101dee
(XEN) gfn: 000f010a mfn: 001b1f8b
(XEN) gfn: 000f010b mfn: 00102973
(XEN) gfn: 000f010c mfn: 001b1f8a
(XEN) gfn: 000f010d mfn: 00102972
(XEN) gfn: 000f010e mfn: 001b1f89
(XEN) gfn: 000f010f mfn: 0010298b
(XEN) gfn: 000f0110 mfn: 001b1f88
(XEN) gfn: 000f0111 mfn: 0010298a
(XEN) gfn: 000f0112 mfn: 001b1f87
(XEN) gfn: 000f0113 mfn: 00100301
(XEN) gfn: 000f0114 mfn: 001b1f86
(XEN) gfn: 000f0115 mfn: 00100300
(XEN) gfn: 000f0116 mfn: 001b1f85
(XEN) gfn: 000f0117 mfn: 001002ff
(XEN) gfn: 000f0118 mfn: 001b1f84
(XEN) gfn: 000f0119 mfn: 001002fe
(XEN) gfn: 000f011a mfn: 001b1f83
(XEN) gfn: 000f011b mfn: 00102803
(XEN) gfn: 000f011c mfn: 001b1f8+2
(XEN) gfn: 000f011d mfn: 00102802
(XEN) gfn: 000f011e mfn: 001b1f81
(XEN) gfn: 000f011f mfn: 0010038f
(XEN) gfn: 000f0120 mfn: 001b1f80
(XEN) gfn: 000f0121 mfn: 0010038e
(XEN) gfn: 000f0122 mfn: 001b06cf
(XEN) gfn: 000f0123 mfn: 00102e23
(XEN) gfn: 000f0124 mfn: 001b06ce
(XEN) gfn: 000f0125 mfn: 00102e22
(XEN) gfn: 000f0126 mfn: 001b06cd
(XEN) gfn: 000f0127 mfn: 0010279b
(XEN) gfn: 000f0128 mfn: 001b06cc
(XEN) gfn: 000f0129 mfn: 0010279a
(XEN) gfn: 000f012a mfn: 001b06cb
(XEN) gfn: 000f012b mfn: 00102c33
(XEN) gfn: 000f012c mfn: 001b06ca
(XEN) gfn: 000f012d mfn: 00102c32
(XEN) gfn: 000f012e mfn: 001b06c9
(XEN) gfn: 000f012f mfn: 001028d7
(XEN) gfn: 000f0130 mfn: 001b06c8
(XEN) gfn: 000f0131 mfn: 001028d6
(XEN) gfn: 000f0132 mfn: 001b06c7
(XEN) gfn: 000f0133 mfn: 00102c6f
(XEN) gfn: 000f0134 mfn: 001b06c6
(XEN) gfn: 000f0135 mfn: 00102c6e
(XEN) gfn: 000f0136 mfn: 001b06c5
(XEN) gfn: 000f0137 mfn: 00102d8f
(XEN) gfn: 000f0138 mfn: 001b06c4
(XEN) gfn: 000f0139 mfn: 00102d8e
(XEN) gfn: 000f013a mfn: 001b06c3
(XEN) gfn: 000f013b mfn: 001018bf
(XEN) gfn: 000f013c mfn: 001b06c2
(XEN) gfn: 000f013d mfn: 001018be
(XEN) gfn: 000f013e mfn: 001b06c1
(XEN) gfn: 000f013f mfn: 00102371
(XEN) gfn: 000f0140 mfn: 001b06c0
(XEN) gfn: 000f0141 mfn: 00102370
(XEN) gfn: 000f0142 mfn: 00162ecf
(XEN) gfn: 000f0143 mfn: 00102ecf
(XEN) gfn: 000f0144 mfn: 00162ece
(XEN) gfn: 000f0145 mfn: 00102ece
(XEN) gfn: 000f0146 mfn: 00162ecd
(XEN) gfn: 000f0147 mfn: 001027a3
(XEN) gfn: 000f0148 mfn: 00162ecc
(XEN) gfn: 000f0149 mfn: 001027a2
(XEN) gfn: 000f014a mfn: 00162ecb
(XEN) gfn: 000f014b mfn: 0010184f
(XEN) gfn: 000f014c mfn: 00162eca
(XEN) gfn: 000f014d mfn: 0010184e
(XEN) gfn: 000f014e mfn: 00162ec9
(XEN) gfn: 000f014f mfn: 0010156b
(XEN) gfn: 000f0150 mfn: 00162ec8
(XEN) gfn: 000f0151 mfn: 0010156a
(XEN) gfn: 000f0152 mfn: 00162ec7
(XEN) gfn: 000f0153 mfn: 00101783
(XEN) gfn: 000f0154 mfn: 00162ec6
(XEN) gfn: 000f0155 mfn: 00101782
(XEN) gfn: 000f0156 mfn: 00162ec5
(XEN) gfn: 000f0157 mfn: 00101365
(XEN) gfn: 000f0158 mfn: 00162ec4
(XEN) gfn: 000f0159 mfn: 00101364
(XEN) gfn: 000f015a mfn: 00162ec3
(XEN) gfn: 000f015b mfn: 00101363
(XEN) gfn: 000f015c mfn: 00162ec2
(XEN) gfn: 000f015d mfn: 00101362
(XEN) gfn: 000f015e mfn: 00162ec1
(XEN) gfn: 000f015f mfn: 00101357
(XEN) gfn: 000f0160 mfn: 00162ec0
(XEN) gfn: 000f0161 mfn: 00101356
(XEN) gfn: 000f0162 mfn: 001632cf
(XEN) gfn: 000f0163 mfn: 00102bd9
(XEN) gfn: 000f0164 mfn: 001632ce
(XEN) gfn: 000f0165 mfn: 00102bd8
(XEN) gfn: 000f0166 mfn: 001632cd
(XEN) gfn: 000f0167 mfn: 001002df
(XEN) gfn: 000f0168 mfn: 001632cc
(XEN) gfn: 000f0169 mfn: 001002de
(XEN) gfn: 000f016a mfn: 001632cb
(XEN) gfn: 000f016b mfn: 00102bcb
(XEN) gfn: 000f016c mfn: 001632ca
(XEN) gfn: 000f016d mfn: 00102bca
(XEN) gfn: 000f016e mfn: 001632c9
(XEN) gfn: 000f016f mfn: 00102e53
(XEN) gfn: 000f0170 mfn: 001632c8
(XEN) gfn: 000f0171 mfn: 00102e52
(XEN) gfn: 000f0172 mfn: 001632c7
(XEN) gfn: 000f0173 mfn: 0010253b
(XEN) gfn: 000f0174 mfn: 001632c6
(XEN) gfn: 000f0175 mfn: 0010253a
(XEN) gfn: 000f0176 mfn: 001632c5
(XEN) gfn: 000f0177 mfn: 0010257d
(XEN) gfn: 000f0178 mfn: 001632c4
(XEN) gfn: 000f0179 mfn: 0010257c
(XEN) gfn: 000f017a mfn: 001632c3
(XEN) gfn: 000f017b mfn: 00102579
(XEN) gfn: 000f017c mfn: 001632c2
(XEN) gfn: 000f017d mfn: 00102578
(XEN) gfn: 000f017e mfn: 001632c1
(XEN) gfn: 000f017f mfn: 001096db
(XEN) gfn: 000f0180 mfn: 001632c0
(XEN) gfn: 000f0181 mfn: 001096da
(XEN) gfn: 000f0182 mfn: 001b06bf
(XEN) gfn: 000f0183 mfn: 00109edb
(XEN) gfn: 000f0184 mfn: 001b06be
(XEN) gfn: 000f0185 mfn: 00109eda
(XEN) gfn: 000f0186 mfn: 001b06bd
(XEN) gfn: 000f0187 mfn: 00102c9b
(XEN) gfn: 000f0188 mfn: 001b06bc
(XEN) gfn: 000f0189 mfn: 00102c9a
(XEN) gfn: 000f018a mfn: 001b06bb
(XEN) gfn: 000f018b mfn: 00102d07
(XEN) gfn: 000f018c mfn: 001b06ba
(XEN) gfn: 000f018d mfn: 00102d06
(XEN) gfn: 000f018e mfn: 001b06b9
(XEN) gfn: 000f018f mfn: 00102d1b
(XEN) gfn: 000f0190 mfn: 001b06b8
(XEN) gfn: 000f0191 mfn: 00102d1a
(XEN) gfn: 000f0192 mfn: 001b06b7
(XEN) gfn: 000f0193 mfn: 00102e2f
(XEN) gfn: 000f0194 mfn: 001b06b6
(XEN) gfn: 000f0195 mfn: 00102e2e
(XEN) gfn: 000f0196 mfn: 001b06b5
(XEN) gfn: 000f0197 mfn: 00101329
(XEN) gfn: 000f0198 mfn: 001b06b4
(XEN) gfn: 000f0199 mfn: 00101328
(XEN) gfn: 000f019a mfn: 001b06b3
(XEN) gfn: 000f019b mfn: 00102d7b
(XEN) gfn: 000f019c mfn: 001b06b2
(XEN) gfn: 000f019d mfn: 00102d7a
(XEN) gfn: 000f019e mfn: 001b06b1
(XEN) gfn: 000f019f mfn: 0010296b
(XEN) gfn: 000f01a0 mfn: 001b06b0
(XEN) gfn: 000f01a1 mfn: 0010296a
(XEN) gfn: 000f01a2 mfn: 001b06af
(XEN) gfn: 000f01a3 mfn: 00102893
(XEN) gfn: 000f01a4 mfn: 001b06ae
(XEN) gfn: 000f01a5 mfn: 00102892
(XEN) gfn: 000f01a6 mfn: 001b06ad
(XEN) gfn: 000f01a7 mfn: 00101897
(XEN) gfn: 000f01a8 mfn: 001b06ac
(XEN) gfn: 000f01a9 mfn: 00101896
(XEN) gfn: 000f01aa mfn: 001b06ab
(XEN) gfn: 000f01ab mfn: 0010246f
(XEN) gfn: 000f01ac mfn: 001b06aa
(XEN) gfn: 000f01ad mfn: 0010246e
(XEN) gfn: 000f01ae mfn: 001b06a9
(XEN) gfn: 000f01af mfn: 00102929
(XEN) gfn: 000f01b0 mfn: 001b06a8
(XEN) gfn: 000f01b1 mfn: 00102928
(XEN) gfn: 000f01b2 mfn: 001b06a7
(XEN) gfn: 000f01b3 mfn: 00102be1
(XEN) gfn: 000f01b4 mfn: 001b06a6
(XEN) gfn: 000f01b5 mfn: 00102be0
(XEN) gfn: 000f01b6 mfn: 001b06a5
(XEN) gfn: 000f01b7 mfn: 00101869
(XEN) gfn: 000f01b8 mfn: 001b06a4
(XEN) gfn: 000f01b9 mfn: 00101868
(XEN) gfn: 000f01ba mfn: 001b06a3
(XEN) gfn: 000f01bb mfn: 0010195f
(XEN) gfn: 000f01bc mfn: 001b06a2
(XEN) gfn: 000f01bd mfn: 0010195e
(XEN) gfn: 000f01be mfn: 001b06a1
(XEN) gfn: 000f01bf mfn: 00102751
(XEN) gfn: 000f01c0 mfn: 001b06a0
(XEN) gfn: 000f01c1 mfn: 00102750
(XEN) gfn: 000f01c2 mfn: 001b069f
(XEN) gfn: 000f01c3 mfn: 0010147f
(XEN) gfn: 000f01c4 mfn: 001b069e
(XEN) gfn: 000f01c5 mfn: 0010147e
(XEN) gfn: 000f01c6 mfn: 001b069d
(XEN) gfn: 000f01c7 mfn: 00101453
(XEN) gfn: 000f01c8 mfn: 001b069c
(XEN) gfn: 000f01c9 mfn: 00101452
(XEN) gfn: 000f01ca mfn: 001b069b
(XEN) gfn: 000f01cb mfn: 0010176d
(XEN) gfn: 000f01cc mfn: 001b069a
(XEN) gfn: 000f01cd mfn: 0010176c
(XEN) gfn: 000f01ce mfn: 001b0699
(XEN) gfn: 000f01cf mfn: 00101511
(XEN) gfn: 000f01d0 mfn: 001b0698
(XEN) gfn: 000f01d1 mfn: 00101510
(XEN) gfn: 000f01d2 mfn: 001b0697
(XEN) gfn: 000f01d3 mfn: 001028b5
(XEN) gfn: 000f01d4 mfn: 001b0696
(XEN) gfn: 000f01d5 mfn: 001028b4
(XEN) gfn: 000f01d6 mfn: 001b0695
(XEN) gfn: 000f01d7 mfn: 00101411
(XEN) gfn: 000f01d8 mfn: 001b0694
(XEN) gfn: 000f01d9 mfn: 00101410
(XEN) gfn: 000f01da mfn: 001b0693
(XEN) gfn: 000f01db mfn: 001015a7
(XEN) gfn: 000f01dc mfn: 001b0692
(XEN) gfn: 000f01dd mfn: 001015a6
(XEN) gfn: 000f01de mfn: 001b0691
(XEN) gfn: 000f01df mfn: 00102cf5
(XEN) gfn: 000f01e0 mfn: 001b0690
(XEN) gfn: 000f01e1 mfn: 00102cf4
(XEN) gfn: 000f01e2 mfn: 001b068f
(XEN) gfn: 000f01e3 mfn: 001027c1
(XEN) gfn: 000f01e4 mfn: 001b068e
(XEN) gfn: 000f01e5 mfn: 001027c0
(XEN) gfn: 000f01e6 mfn: 001b068d
(XEN) gfn: 000f01e7 mfn: 00100533
(XEN) gfn: 000f01e8 mfn: 001b068c
(XEN) gfn: 000f01e9 mfn: 00100532
(XEN) gfn: 000f01ea mfn: 001b068b
(XEN) gfn: 000f01eb mfn: 00102e95
(XEN) gfn: 000f01ec mfn: 001b068a
(XEN) gfn: 000f01ed mfn: 00102e94
(XEN) gfn: 000f01ee mfn: 001b0689
(XEN) gfn: 000f01ef mfn: 00101491
(XEN) gfn: 000f01f0 mfn: 001b0688
(XEN) gfn: 000f01f1 mfn: 00101490
(XEN) gfn: 000f01f2 mfn: 001b0687
(XEN) gfn: 000f01f3 mfn: 0010130d
(XEN) gfn: 000f01f4 mfn: 001b0686
(XEN) gfn: 000f01f5 mfn: 0010130c
(XEN) gfn: 000f01f6 mfn: 001b0685
(XEN) gfn: 000f01f7 mfn: 00101715
(XEN) gfn: 000f01f8 mfn: 001b0684
(XEN) gfn: 000f01f9 mfn: 00101714
(XEN) gfn: 000f01fa mfn: 001b0683
(XEN) gfn: 000f01fb mfn: 00101399
(XEN) gfn: 000f01fc mfn: 001b0682
(XEN) gfn: 000f01fd mfn: 00101398
(XEN) gfn: 000f01fe mfn: 001b0681
(XEN) gfn: 000f01ff mfn: 00101e83
(XEN) gfn: 000f0200 mfn: 001b0680
(XEN) gfn: 000f0201 mfn: 00101e82
(XEN) gfn: 000f0202 mfn: 00162ebf
(XEN) gfn: 000f0203 mfn: 001013a9
(XEN) gfn: 000f0204 mfn: 00162ebe
(XEN) gfn: 000f0205 mfn: 001013a8
(XEN) gfn: 000f0206 mfn: 00162ebd
(XEN) gfn: 000f0207 mfn: 00102883
(XEN) gfn: 000f0208 mfn: 00162ebc
(XEN) gfn: 000f0209 mfn: 00102882
(XEN) gfn: 000f020a mfn: 00162ebb
(XEN) gfn: 000f020b mfn: 00102945
(XEN) gfn: 000f020c mfn: 00162eba
(XEN) gfn: 000f020d mfn: 00102944
(XEN) gfn: 000f020e mfn: 00162eb9
(XEN) gfn: 000f020f mfn: 00101ac3
(XEN) gfn: 000f0210 mfn: 00162eb8
(XEN) gfn: 000f0211 mfn: 00101ac2
(XEN) gfn: 000f0212 mfn: 00162eb7
(XEN) gfn: 000f0213 mfn: 00101ac1
(XEN) gfn: 000f0214 mfn: 00162eb6
(XEN) gfn: 000f0215 mfn: 00101ac0
(XEN) gfn: 000f0216 mfn: 00162eb5
(XEN) gfn: 000f0217 mfn: 00101747
(XEN) gfn: 000f0218 mfn: 00162eb4
(XEN) gfn: 000f0219 mfn: 00101746
(XEN) gfn: 000f021a mfn: 00162eb3
(XEN) gfn: 000f021b mfn: 00101745
(XEN) gfn: 000f021c mfn: 00162eb2
(XEN) gfn: 000f021d mfn: 00101744
(XEN) gfn: 000f021e mfn: 00162eb1
(XEN) gfn: 000f021f mfn: 001029f7
(XEN) gfn: 000f0220 mfn: 00162eb0
(XEN) gfn: 000f0221 mfn: 001029f6
(XEN) gfn: 000f0222 mfn: 00162eaf
(XEN) gfn: 000f0223 mfn: 001029f5
(XEN) gfn: 000f0224 mfn: 00162eae
(XEN) gfn: 000f0225 mfn: 001029f4
(XEN) gfn: 000f0226 mfn: 00162ead
(XEN) gfn: 000f0227 mfn: 00102d37
(XEN) gfn: 000f0228 mfn: 00162eac
(XEN) gfn: 000f0229 mfn: 00102d36
(XEN) gfn: 000f022a mfn: 00162eab
(XEN) gfn: 000f022b mfn: 00102d35
(XEN) gfn: 000f022c mfn: 00162eaa
(XEN) gfn: 000f022d mfn: 00102d34
(XEN) gfn: 000f022e mfn: 00162ea9
(XEN) gfn: 000f022f mfn: 00102737
(XEN) gfn: 000f0230 mfn: 00162ea8
(XEN) gfn: 000f0231 mfn: 00102736
(XEN) gfn: 000f0232 mfn: 00162ea7
(XEN) gfn: 000f0233 mfn: 00102735
(XEN) gfn: 000f0234 mfn: 00162ea6
(XEN) gfn: 000f0235 mfn: 00102734
(XEN) gfn: 000f0236 mfn: 00162ea5
(XEN) gfn: 000f0237 mfn: 001019db
(XEN) gfn: 000f0238 mfn: 00162ea4
(XEN) gfn: 000f0239 mfn: 001019da
(XEN) gfn: 000f023a mfn: 00162ea3
(XEN) gfn: 000f023b mfn: 001019d9
(XEN) gfn: 000f023c mfn: 00162ea2
(XEN) gfn: 000f023d mfn: 001019d8
(XEN) gfn: 000f023e mfn: 00162ea1
(XEN) gfn: 000f023f mfn: 00101d9b
(XEN) gfn: 000f0240 mfn: 00162ea0
(XEN) gfn: 000f0241 mfn: 00101d9a
(XEN) gfn: 000f0242 mfn: 00162e9f
(XEN) gfn: 000f0243 mfn: 00101d99
(XEN) gfn: 000f0244 mfn: 00162e9e
(XEN) gfn: 000f0245 mfn: 00101d98
(XEN) gfn: 000f0246 mfn: 00162e9d
(XEN) gfn: 000f0247 mfn: 00101777
(XEN) gfn: 000f0248 mfn: 00162e9c
(XEN) gfn: 000f0249 mfn: 00101776
(XEN) gfn: 000f024a mfn: 00162e9b
(XEN) gfn: 000f024b mfn: 00101775
(XEN) gfn: 000f024c mfn: 00162e9a
(XEN) gfn: 000f024d mfn: 00101774
(XEN) gfn: 000f024e mfn: 00162e99
(XEN) gfn: 000f024f mfn: 00102927
(XEN) gfn: 000f0250 mfn: 00162e98
(XEN) gfn: 000f0251 mfn: 00102926
(XEN) gfn: 000f0252 mfn: 00162e97
(XEN) gfn: 000f0253 mfn: 00102925
(XEN) gfn: 000f0254 mfn: 00162e96
(XEN) gfn: 000f0255 mfn: 00102924
(XEN) gfn: 000f0256 mfn: 00162e95
(XEN) gfn: 000f0257 mfn: 00101563
(XEN) gfn: 000f0258 mfn: 00162e94
(XEN) gfn: 000f0259 mfn: 00101562
(XEN) gfn: 000f025a mfn: 00162e93
(XEN) gfn: 000f025b mfn: 00101561
(XEN) gfn: 000f025c mfn: 00162e92
(XEN) gfn: 000f025d mfn: 00101560
(XEN) gfn: 000f025e mfn: 00162e91
(XEN) gfn: 000f025f mfn: 00102d83
(XEN) gfn: 000f0260 mfn: 00162e90
(XEN) gfn: 000f0261 mfn: 00102d82
(XEN) gfn: 000f0262 mfn: 00162e8f
(XEN) gfn: 000f0263 mfn: 00102d81
(XEN) gfn: 000f0264 mfn: 00162e8e
(XEN) gfn: 000f0265 mfn: 00102d80
(XEN) gfn: 000f0266 mfn: 00162e8d
(XEN) gfn: 000f0267 mfn: 00102d7f
(XEN) gfn: 000f0268 mfn: 00162e8c
(XEN) gfn: 000f0269 mfn: 00102d7e
(XEN) gfn: 000f026a mfn: 00162e8b
(XEN) gfn: 000f026b mfn: 00102d7d
(XEN) gfn: 000f026c mfn: 00162e8a
(XEN) gfn: 000f026d mfn: 00102d7c
(XEN) gfn: 000f026e mfn: 00162e89
(XEN) gfn: 000f026f mfn: 00102ccf
(XEN) gfn: 000f0270 mfn: 00162e88
(XEN) gfn: 000f0271 mfn: 00102cce
(XEN) gfn: 000f0272 mfn: 00162e87
(XEN) gfn: 000f0273 mfn: 00102ccd
(XEN) gfn: 000f0274 mfn: 00162e86
(XEN) gfn: 000f0275 mfn: 00102ccc
(XEN) gfn: 000f0276 mfn: 00162e85
(XEN) gfn: 000f0277 mfn: 001029fb
(XEN) gfn: 000f0278 mfn: 00162e84
(XEN) gfn: 000f0279 mfn: 001029fa
(XEN) gfn: 000f027a mfn: 00162e83
(XEN) gfn: 000f027b mfn: 001029f9
(XEN) gfn: 000f027c mfn: 00162e82
(XEN) gfn: 000f027d mfn: 001029f8
(XEN) gfn: 000f027e mfn: 00162e81
(XEN) gfn: 000f027f mfn: 001004b7
(XEN) gfn: 000f0280 mfn: 00162e80
(XEN) gfn: 000f0281 mfn: 001004b6
(XEN) gfn: 000f0282 mfn: 001632bf
(XEN) gfn: 000f0283 mfn: 001004b5
(XEN) gfn: 000f0284 mfn: 001632be
(XEN) gfn: 000f0285 mfn: 001004b4
(XEN) gfn: 000f0286 mfn: 001632bd
(XEN) gfn: 000f0287 mfn: 00101307
(XEN) gfn: 000f0288 mfn: 001632bc
(XEN) gfn: 000f0289 mfn: 00101306
(XEN) gfn: 000f028a mfn: 001632bb
(XEN) gfn: 000f028b mfn: 00101305
(XEN) gfn: 000f028c mfn: 001632ba
(XEN) gfn: 000f028d mfn: 00101304
(XEN) gfn: 000f028e mfn: 001632b9
(XEN) gfn: 000f028f mfn: 0010130b
(XEN) gfn: 000f0290 mfn: 001632b8
(XEN) gfn: 000f0291 mfn: 0010130a
(XEN) gfn: 000f0292 mfn: 001632b7
(XEN) gfn: 000f0293 mfn: 00101309
(XEN) gfn: 000f0294 mfn: 001632b6
(XEN) gfn: 000f0295 mfn: 00101308
(XEN) gfn: 000f0296 mfn: 001632b5
(XEN) gfn: 000f0297 mfn: 00102e57
(XEN) gfn: 000f0298 mfn: 001632b4
(XEN) gfn: 000f0299 mfn: 00102e56
(XEN) gfn: 000f029a mfn: 001632b3
(XEN) gfn: 000f029b mfn: 00102e55
(XEN) gfn: 000f029c mfn: 001632b2
(XEN) gfn: 000f029d mfn: 00102e54
(XEN) gfn: 000f029e mfn: 001632b1
(XEN) gfn: 000f029f mfn: 0010266f
(XEN) gfn: 000f02a0 mfn: 001632b0
(XEN) gfn: 000f02a1 mfn: 0010266e
(XEN) gfn: 000f02a2 mfn: 001632af
(XEN) gfn: 000f02a3 mfn: 0010266d
(XEN) gfn: 000f02a4 mfn: 001632ae
(XEN) gfn: 000f02a5 mfn: 0010266c
(XEN) gfn: 000f02a6 mfn: 001632ad
(XEN) gfn: 000f02a7 mfn: 001017a7
(XEN) gfn: 000f02a8 mfn: 001632ac
(XEN) gfn: 000f02a9 mfn: 001017a6
(XEN) gfn: 000f02aa mfn: 001632ab
(XEN) gfn: 000f02ab mfn: 001017a5
(XEN) gfn: 000f02ac mfn: 001632aa
(XEN) gfn: 000f02ad mfn: 001017a4
(XEN) gfn: 000f02ae mfn: 001632a9
(XEN) gfn: 000f02af mfn: 001096df
(XEN) gfn: 000f02b0 mfn: 001632a8
(XEN) gfn: 000f02b1 mfn: 001096de
(XEN) gfn: 000f02b2 mfn: 001632a7
(XEN) gfn: 000f02b3 mfn: 001096dd
(XEN) gfn: 000f02b4 mfn: 001632a6
(XEN) gfn: 000f02b5 mfn: 001096dc
(XEN) gfn: 000f02b6 mfn: 001632a5
(XEN) gfn: 000f02b7 mfn: 00109edf
(XEN) gfn: 000f02b8 mfn: 001632a4
(XEN) gfn: 000f02b9 mfn: 00109ede
(XEN) gfn: 000f02ba mfn: 001632a3
(XEN) gfn: 000f02bb mfn: 00109edd
(XEN) gfn: 000f02bc mfn: 001632a2
(XEN) gfn: 000f02bd mfn: 00109edc
(XEN) gfn: 000f02be mfn: 001632a1
(XEN) gfn: 000f02bf mfn: 001025ef
(XEN) gfn: 000f02c0 mfn: 001632a0
(XEN) gfn: 000f02c1 mfn: 001025ee
(XEN) gfn: 000f02c2 mfn: 0016329f
(XEN) gfn: 000f02c3 mfn: 001025ed
(XEN) gfn: 000f02c4 mfn: 0016329e
(XEN) gfn: 000f02c5 mfn: 001025ec
(XEN) gfn: 000f02c6 mfn: 0016329d
(XEN) gfn: 000f02c7 mfn: 00102bd7
(XEN) gfn: 000f02c8 mfn: 0016329c
(XEN) gfn: 000f02c9 mfn: 00102bd6
(XEN) gfn: 000f02ca mfn: 0016329b
(XEN) gfn: 000f02cb mfn: 00102bd5
(XEN) gfn: 000f02cc mfn: 0016329a
(XEN) gfn: 000f02cd mfn: 00102bd4
(XEN) gfn: 000f02ce mfn: 00163299
(XEN) gfn: 000f02cf mfn: 00101e97
(XEN) gfn: 000f02d0 mfn: 00163298
(XEN) gfn: 000f02d1 mfn: 00101e96
(XEN) gfn: 000f02d2 mfn: 00163297
(XEN) gfn: 000f02d3 mfn: 00101e95
(XEN) gfn: 000f02d4 mfn: 00163296
(XEN) gfn: 000f02d5 mfn: 00101e94
(XEN) gfn: 000f02d6 mfn: 00163295
(XEN) gfn: 000f02d7 mfn: +00101e4f
(XEN) gfn: 000f02d8 mfn: 00163294
(XEN) gfn: 000f02d9 mfn: 00101e4e
(XEN) gfn: 000f02da mfn: 00163293
(XEN) gfn: 000f02db mfn: 00101e4d
(XEN) gfn: 000f02dc mfn: 00163292
(XEN) gfn: 000f02dd mfn: 00101e4c
(XEN) gfn: 000f02de mfn: 00163291
(XEN) gfn: 000f02df mfn: 00101abf
(XEN) gfn: 000f02e0 mfn: 00163290
(XEN) gfn: 000f02e1 mfn: 00101abe
(XEN) gfn: 000f02e2 mfn: 0016328f
(XEN) gfn: 000f02e3 mfn: 00101abd
(XEN) gfn: 000f02e4 mfn: 0016328e
(XEN) gfn: 000f02e5 mfn: 00101abc
(XEN) gfn: 000f02e6 mfn: 0016328d
(XEN) gfn: 000f02e7 mfn: 00102bcf
(XEN) gfn: 000f02e8 mfn: 0016328c
(XEN) gfn: 000f02e9 mfn: 00102bce
(XEN) gfn: 000f02ea mfn: 0016328b
(XEN) gfn: 000f02eb mfn: 00102bcd
(XEN) gfn: 000f02ec mfn: 0016328a
(XEN) gfn: 000f02ed mfn: 00102bcc
(XEN) gfn: 000f02ee mfn: 00163289
(XEN) gfn: 000f02ef mfn: 00102e7f
(XEN) gfn: 000f02f0 mfn: 00163288
(XEN) gfn: 000f02f1 mfn: 00102e7e
(XEN) gfn: 000f02f2 mfn: 00163287
(XEN) gfn: 000f02f3 mfn: 00102e7d
(XEN) gfn: 000f02f4 mfn: 00163286
(XEN) gfn: 000f02f5 mfn: 00102e7c
(XEN) gfn: 000f02f6 mfn: 00163285
(XEN) gfn: 000f02f7 mfn: 0010134b
(XEN) gfn: 000f02f8 mfn: 00163284
(XEN) gfn: 000f02f9 mfn: 0010134a
(XEN) gfn: 000f02fa mfn: 00163283
(XEN) gfn: 000f02fb mfn: 00101349
(XEN) gfn: 000f02fc mfn: 00163282
(XEN) gfn: 000f02fd mfn: 00101348
(XEN) gfn: 000f02fe mfn: 00163281
(XEN) gfn: 000f02ff mfn: 0010275b
(XEN) gfn: 000f0300 mfn: 00163280
(XEN) gfn: 000f0301 mfn: 0010275a
(XEN) gfn: 000f0302 mfn: 001630ff
(XEN) gfn: 000f0303 mfn: 00102759
(XEN) gfn: 000f0304 mfn: 001630fe
(XEN) gfn: 000f0305 mfn: 00102758
(XEN) gfn: 000f0306 mfn: 001630fd
(XEN) gfn: 000f0307 mfn: 00102df3
(XEN) gfn: 000f0308 mfn: 001630fc
(XEN) gfn: 000f0309 mfn: 00102df2
(XEN) gfn: 000f030a mfn: 001630fb
(XEN) gfn: 000f030b mfn: 00102df1
(XEN) gfn: 000f030c mfn: 001630fa
(XEN) gfn: 000f030d mfn: 00102df0
(XEN) gfn: 000f030e mfn: 001630f9
(XEN) gfn: 000f030f mfn: 001012df
(XEN) gfn: 000f0310 mfn: 001630f8
(XEN) gfn: 000f0311 mfn: 001012de
(XEN) gfn: 000f0312 mfn: 001630f7
(XEN) gfn: 000f0313 mfn: 001012dd
(XEN) gfn: 000f0314 mfn: 001630f6
(XEN) gfn: 000f0315 mfn: 001012dc
(XEN) gfn: 000f0316 mfn: 001630f5
(XEN) gfn: 000f0317 mfn: 0010035b
(XEN) gfn: 000f0318 mfn: 001630f4
(XEN) gfn: 000f0319 mfn: 0010035a
(XEN) gfn: 000f031a mfn: 001630f3
(XEN) gfn: 000f031b mfn: 00100359
(XEN) gfn: 000f031c mfn: 001630f2
(XEN) gfn: 000f031d mfn: 00100358
(XEN) gfn: 000f031e mfn: 001630f1
(XEN) gfn: 000f031f mfn: 001025e7
(XEN) gfn: 000f0320 mfn: 001630f0
(XEN) gfn: 000f0321 mfn: 001025e6
(XEN) gfn: 000f0322 mfn: 001630ef
(XEN) gfn: 000f0323 mfn: 001025e5
(XEN) gfn: 000f0324 mfn: 001630ee
(XEN) gfn: 000f0325 mfn: 001025e4
(XEN) gfn: 000f0326 mfn: 001630ed
(XEN) gfn: 000f0327 mfn: 001025e3
(XEN) gfn: 000f0328 mfn: 001630ec
(XEN) gfn: 000f0329 mfn: 001025e2
(XEN) gfn: 000f032a mfn: 001630eb
(XEN) gfn: 000f032b mfn: 001025e1
(XEN) gfn: 000f032c mfn: 001630ea
(XEN) gfn: 000f032d mfn: 001025e0
(XEN) gfn: 000f032e mfn: 001630e9
(XEN) gfn: 000f032f mfn: 00102677
(XEN) gfn: 000f0330 mfn: 001630e8
(XEN) gfn: 000f0331 mfn: 00102676
(XEN) gfn: 000f0332 mfn: 001630e7
(XEN) gfn: 000f0333 mfn: 00102675
(XEN) gfn: 000f0334 mfn: 001630e6
(XEN) gfn: 000f0335 mfn: 00102674
(XEN) gfn: 000f0336 mfn: 001630e5
(XEN) gfn: 000f0337 mfn: 00102673
(XEN) gfn: 000f0338 mfn: 001630e4
(XEN) gfn: 000f0339 mfn: 00102672
(XEN) gfn: 000f033a mfn: 001630e3
(XEN) gfn: 000f033b mfn: 00102671
(XEN) gfn: 000f033c mfn: 001630e2
(XEN) gfn: 000f033d mfn: 00102670
(XEN) gfn: 000f033e mfn: 001630e1
(XEN) gfn: 000f033f mfn: 00102347
(XEN) gfn: 000f0340 mfn: 001630e0
(XEN) gfn: 000f0341 mfn: 00102346
(XEN) gfn: 000f0342 mfn: 001630df
(XEN) gfn: 000f0343 mfn: 00102345
(XEN) gfn: 000f0344 mfn: 001630de
(XEN) gfn: 000f0345 mfn: 00102344
(XEN) gfn: 000f0346 mfn: 001630dd
(XEN) gfn: 000f0347 mfn: 00102343
(XEN) gfn: 000f0348 mfn: 001630dc
(XEN) gfn: 000f0349 mfn: 00102342
(XEN) gfn: 000f034a mfn: 001630db
(XEN) gfn: 000f034b mfn: 00102341
(XEN) gfn: 000f034c mfn: 001630da
(XEN) gfn: 000f034d mfn: 00102340
(XEN) gfn: 000f034e mfn: 001630d9
(XEN) gfn: 000f034f mfn: 00109817
(XEN) gfn: 000f0350 mfn: 001630d8
(XEN) gfn: 000f0351 mfn: 00109816
(XEN) gfn: 000f0352 mfn: 001630d7
(XEN) gfn: 000f0353 mfn: 00109815
(XEN) gfn: 000f0354 mfn: 001630d6
(XEN) gfn: 000f0355 mfn: 00109814
(XEN) gfn: 000f0356 mfn: 001630d5
(XEN) gfn: 000f0357 mfn: 00109813
(XEN) gfn: 000f0358 mfn: 001630d4
(XEN) gfn: 000f0359 mfn: 00109812
(XEN) gfn: 000f035a mfn: 001630d3
(XEN) gfn: 000f035b mfn: 00109811
(XEN) gfn: 000f035c mfn: 001630d2
(XEN) gfn: 000f035d mfn: 00109810
(XEN) gfn: 000f035e mfn: 001630d1
(XEN) gfn: 000f035f mfn: 0010224f
(XEN) gfn: 000f0360 mfn: 001630d0
(XEN) gfn: 000f0361 mfn: 0010224e
(XEN) gfn: 000f0362 mfn: 001630cf
(XEN) gfn: 000f0363 mfn: 0010224d
(XEN) gfn: 000f0364 mfn: 001630ce
(XEN) gfn: 000f0365 mfn: 0010224c
(XEN) gfn: 000f0366 mfn: 001630cd
(XEN) gfn: 000f0367 mfn: 0010224b
(XEN) gfn: 000f0368 mfn: 001630cc
(XEN) gfn: 000f0369 mfn: 0010224a
(XEN) gfn: 000f036a mfn: 001630cb
(XEN) gfn: 000f036b mfn: 00102249
(XEN) gfn: 000f036c mfn: 001630ca
(XEN) gfn: 000f036d mfn: 00102248
(XEN) gfn: 000f036e mfn: 001630c9
(XEN) gfn: 000f036f mfn: 00102247
(XEN) gfn: 000f0370 mfn: 001630c8
(XEN) gfn: 000f0371 mfn: 00102246
(XEN) gfn: 000f0372 mfn: 001630c7
(XEN) gfn: 000f0373 mfn: 00102245
(XEN) gfn: 000f0374 mfn: 001630c6
(XEN) gfn: 000f0375 mfn: 00102244
(XEN) gfn: 000f0376 mfn: 001630c5
(XEN) gfn: 000f0377 mfn: 00102243
(XEN) gfn: 000f0378 mfn: 001630c4
(XEN) gfn: 000f0379 mfn: 00102242
(XEN) gfn: 000f037a mfn: 001630c3
(XEN) gfn: 000f037b mfn: 00102241
(XEN) gfn: 000f037c mfn: 001630c2
(XEN) gfn: 000f037d mfn: 00102240
(XEN) gfn: 000f037e mfn: 001630c1
(XEN) gfn: 000f037f mfn: 0010980f
(XEN) gfn: 000f0380 mfn: 001630c0
(XEN) gfn: 000f0381 mfn: 0010980e
(XEN) gfn: 000f0382 mfn: 001b067f
(XEN) gfn: 000f0383 mfn: 0010980d
(XEN) gfn: 000f0384 mfn: 001b067e
(XEN) gfn: 000f0385 mfn: 0010980c
(XEN) gfn: 000f0386 mfn: 001b067d
(XEN) gfn: 000f0387 mfn: 0010980b
(XEN) gfn: 000f0388 mfn: 001b067c
(XEN) gfn: 000f0389 mfn: 0010980a
(XEN) gfn: 000f038a mfn: 001b067b
(XEN) gfn: 000f038b mfn: 00109809
(XEN) gfn: 000f038c mfn: 001b067a
(XEN) gfn: 000f038d mfn: 00109808
(XEN) gfn: 000f038e mfn: 001b0679
(XEN) gfn: 000f038f mfn: 00109807
(XEN) gfn: 000f0390 mfn: 001b0678
(XEN) gfn: 000f0391 mfn: 00109806
(XEN) gfn: 000f0392 mfn: 001b0677
(XEN) gfn: 000f0393 mfn: 00109805
(XEN) gfn: 000f0394 mfn: 001b0676
(XEN) gfn: 000f0395 mfn: 00109804
(XEN) gfn: 000f0396 mfn: 001b0675
(XEN) gfn: 000f0397 mfn: 00109803
(XEN) gfn: 000f0398 mfn: 001b0674
(XEN) gfn: 000f0399 mfn: 00109802
(XEN) gfn: 000f039a mfn: 001b0673
(XEN) gfn: 000f039b mfn: 00109801
(XEN) gfn: 000f039c mfn: 001b0672
(XEN) gfn: 000f039d mfn: 00109800
(XEN) gfn: 000f039e mfn: 001b0671
(XEN) gfn: 000f039f mfn: 001025ff
(XEN) gfn: 000f03a0 mfn: 001b0670
(XEN) gfn: 000f03a1 mfn: 001025fe
(XEN) gfn: 000f03a2 mfn: 001b066f
(XEN) gfn: 000f03a3 mfn: 001025fd
(XEN) gfn: 000f03a4 mfn: 001b066e
(XEN) gfn: 000f03a5 mfn: 001025fc
(XEN) gfn: 000f03a6 mfn: 001b066d
(XEN) gfn: 000f03a7 mfn: 001025fb
(XEN) gfn: 000f03a8 mfn: 001b066c
(XEN) gfn: 000f03a9 mfn: 001025fa
(XEN) gfn: 000f03aa mfn: 001b066b
(XEN) gfn: 000f03ab mfn: 001025f9
(XEN) gfn: 000f03ac mfn: 001b066a
(XEN) gfn: 000f03ad mfn: 001025f8
(XEN) gfn: 000f03ae mfn: 001b0669
(XEN) gfn: 000f03af mfn: 001025f7
(XEN) gfn: 000f03b0 mfn: 001b0668
(XEN) gfn: 000f03b1 mfn: 001025f6
(XEN) gfn: 000f03b2 mfn: 001b0667
(XEN) gfn: 000f03b3 mfn: 001025f5
(XEN) gfn: 000f03b4 mfn: 001b0666
(XEN) gfn: 000f03b5 mfn: 001025f4
(XEN) gfn: 000f03b6 mfn: 001b0665
(XEN) gfn: 000f03b7 mfn: 001025f3
(XEN) gfn: 000f03b8 mfn: 001b0664
(XEN) gfn: 000f03b9 mfn: 001025f2
(XEN) gfn: 000f03ba mfn: 001b0663
(XEN) gfn: 000f03bb mfn: 001025f1
(XEN) gfn: 000f03bc mfn: 001b0662
(XEN) gfn: 000f03bd mfn: 001025f0
(XEN) gfn: 000f03be mfn: 001b0661
(XEN) gfn: 000f03bf mfn: 001025df
(XEN) gfn: 000f03c0 mfn: 001b0660
(XEN) gfn: 000f03c1 mfn: 001025de
(XEN) gfn: 000f03c2 mfn: 001b065f
(XEN) gfn: 000f03c3 mfn: 001025dd
(XEN) gfn: 000f03c4 mfn: 001b065e
(XEN) gfn: 000f03c5 mfn: 001025dc
(XEN) gfn: 000f03c6 mfn: 001b065d
(XEN) gfn: 000f03c7 mfn: 001025db
(XEN) gfn: 000f03c8 mfn: 001b065c
(XEN) gfn: 000f03c9 mfn: 001025da
(XEN) gfn: 000f03ca mfn: 001b065b
(XEN) gfn: 000f03cb mfn: 001025d9
(XEN) gfn: 000f03cc mfn: 001b065a
(XEN) gfn: 000f03cd mfn: 001025d8
(XEN) gfn: 000f03ce mfn: 001b0659
(XEN) gfn: 000f03cf mfn: 001025d7
(XEN) gfn: 000f03d0 mfn: 001b0658
(XEN) gfn: 000f03d1 mfn: 001025d6
(XEN) gfn: 000f03d2 mfn: 001b0657
(XEN) gfn: 000f03d3 mfn: 001025d5
(XEN) gfn: 000f03d4 mfn: 001b0656
(XEN) gfn: 000f03d5 mfn: 001025d4
(XEN) gfn: 000f03d6 mfn: 001b0655
(XEN) gfn: 000f03d7 mfn: 001025d3
(XEN) gfn: 000f03d8 mfn: 001b0654
(XEN) gfn: 000f03d9 mfn: 001025d2
(XEN) gfn: 000f03da mfn: 001b0653
(XEN) gfn: 000f03db mfn: 001025d1
(XEN) gfn: 000f03dc mfn: 001b0652
(XEN) gfn: 000f03dd mfn: 001025d0
(XEN) gfn: 000f03de mfn: 001b0651
(XEN) gfn: 000f03df mfn: 001025cf
(XEN) gfn: 000f03e0 mfn: 001b0650
(XEN) gfn: 000f03e1 mfn: 001025ce
(XEN) gfn: 000f03e2 mfn: 001b064f
(XEN) gfn: 000f03e3 mfn: 001025cd
(XEN) gfn: 000f03e4 mfn: 001b064e
(XEN) gfn: 000f03e5 mfn: 001025cc
(XEN) gfn: 000f03e6 mfn: 001b064d
(XEN) gfn: 000f03e7 mfn: 001025cb
(XEN) gfn: 000f03e8 mfn: 001b064c
(XEN) gfn: 000f03e9 mfn: 001025ca
(XEN) gfn: 000f03ea mfn: 001b064b
(XEN) gfn: 000f03eb mfn: 001025c9
(XEN) gfn: 000f03ec mfn: 001b064a
(XEN) gfn: 000f03ed mfn: 001025c8
(XEN) gfn: 000f03ee mfn: 001b0649
(XEN) gfn: 000f03ef mfn: 001025c7
(XEN) gfn: 000f03f0 mfn: 001b0648
(XEN) gfn: 000f03f1 mfn: 001025c6
(XEN) gfn: 000f03f2 mfn: 001b0647
(XEN) gfn: 000f03f3 mfn: 001025c5
(XEN) gfn: 000f03f4 mfn: 001b0646
(XEN) gfn: 000f03f5 mfn: 001025c4
(XEN) gfn: 000f03f6 mfn: 001b0645
(XEN) gfn: 000f03f7 mfn: 001025c3
(XEN) gfn: 000f03f8 mfn: 001b0644
(XEN) gfn: 000f03f9 mfn: 001025c2
(XEN) gfn: 000f03fa mfn: 001b0643
(XEN) gfn: 000f03fb mfn: 001025c1
(XEN) gfn: 000f03fc mfn: 001b0642
(XEN) gfn: 000f03fd mfn: 001025c0
(XEN) gfn: 000f03fe mfn: 001b0641
(XEN) gfn: 000f03ff mfn: 001022ff
(XEN) gfn: 000fc000 mfn: 001b063d
(XEN) gfn: 000fc001 mfn: 001b0640
(XEN) gfn: 000fc002 mfn: 001096f5
(XEN) gfn: 000fc003 mfn: 001b063e
(XEN) gfn: 000fc004 mfn: 001096f4
(XEN) gfn: 000fc005 mfn: 001096f3
(XEN) gfn: 000fc006 mfn: 001b063c
(XEN) gfn: 000fc007 mfn: 001096f2
(XEN) gfn: 000fc008 mfn: 001b063b
(XEN) gfn: 000fc009 mfn: 001096f1
(XEN) gfn: 000fc00a mfn: 001b063a
(XEN) gfn: 000fc00b mfn: 001096f0
(XEN) gfn: 000fc00c mfn: 001b0639
(XEN) gfn: 000fc00d mfn: 001096ef
(XEN) gfn: 000fc00e mfn: 001b0638
(XEN) gfn: 000fc00f mfn: 001096ee
(XEN) gfn: 000fc010 mfn: 001b0637
(XEN) gfn: 000feffa mfn: 000812b9
(XEN) gfn: 000feffb mfn: 0010275d
(XEN) gfn: 000feffc mfn: 00218e10
(XEN) gfn: 000feffd mfn: 0010275c
(XEN) gfn: 000feffe mfn: 00218e0f
(XEN) gfn: 000fefff mfn: 0010049f
(XEN) gfn: 00100000 mfn: 001ba800
(XEN) gfn: 00100200 mfn: 001ba600
(XEN) gfn: 00100400 mfn: 001ba400
(XEN) gfn: 00100600 mfn: 001ba200
(XEN) gfn: 00100800 mfn: 001ba000
(XEN) gfn: 00100a00 mfn: 001b9e00
(XEN) gfn: 00100c00 mfn: 001b9c00
(XEN) gfn: 00100e00 mfn: 001b9a00
(XEN) gfn: 00101000 mfn: 001b9800
(XEN) gfn: 00101200 mfn: 001b9600
(XEN) gfn: 00101400 mfn: 001b9400
(XEN) gfn: 00101600 mfn: 001b9200
(XEN) gfn: 00101800 mfn: 001b9000
(XEN) gfn: 00101a00 mfn: 001b8e00
(XEN) gfn: 00101c00 mfn: 001b8c00
(XEN) gfn: 00101e00 mfn: 001b8a00
(XEN) gfn: 00102000 mfn: 001b8800
(XEN) gfn: 00102200 mfn: 001b8600
(XEN) gfn: 00102400 mfn: 001b8400
(XEN) gfn: 00102600 mfn: 001b8200
(XEN) gfn: 00102800 mfn: 001b8000
(XEN) gfn: 00102a00 mfn: 001afe00
(XEN) gfn: 00102c00 mfn: 001afc00
(XEN) gfn: 00102e00 mfn: 001afa00
(XEN) gfn: 00103000 mfn: 001af800
(XEN) gfn: 00103200 mfn: 001af600
(XEN) gfn: 00103400 mfn: 001af400
(XEN) gfn: 00103600 mfn: 001af200
(XEN) gfn: 00103800 mfn: 001af000
(XEN) gfn: 00103a00 mfn: 001aee00
(XEN) gfn: 00103c00 mfn: 001aec00
(XEN) gfn: 00103e00 mfn: 001aea00
(XEN) gfn: 00104000 mfn: 001ae800
(XEN) gfn: 00104200 mfn: 001ae600
(XEN) gfn: 00104400 mfn: 001ae400
(XEN) gfn: 00104600 mfn: 001ae200
(XEN) gfn: 00104800 mfn: 001ae000
(XEN) gfn: 00104a00 mfn: 001ade00
(XEN) gfn: 00104c00 mfn: 001adc00
(XEN) gfn: 00104e00 mfn: 001ada00
(XEN) gfn: 00105000 mfn: 001ad800
(XEN) gfn: 00105200 mfn: 001ad600
(XEN) gfn: 00105400 mfn: 001ad400
(XEN) gfn: 00105600 mfn: 001ad200
(XEN) gfn: 00105800 mfn: 001ad000
(XEN) gfn: 00105a00 mfn: 001ace00
(XEN) gfn: 00105c00 mfn: 001acc00
(XEN) gfn: 00105e00 mfn: 001aca00
(XEN) gfn: 00106000 mfn: 001ac800
(XEN) gfn: 00106200 mfn: 001ac600
(XEN) gfn: 00106400 mfn: 001ac400
(XEN) gfn: 00106600 mfn: 001ac200
(XEN) gfn: 00106800 mfn: 001ac000
(XEN) gfn: 00106a00 mfn: 001abe00
(XEN) gfn: 00106c00 mfn: 001abc00
(XEN) gfn: 00106e00 mfn: 001aba00
(XEN) gfn: 00107000 mfn: 001ab800
(XEN) gfn: 00107200 mfn: 001ab600
(XEN) gfn: 00107400 mfn: 001ab400
(XEN) gfn: 00107600 mfn: 001ab200
(XEN) gfn: 00107800 mfn: 001ab000
(XEN) gfn: 00107a00 mfn: 001aae00
(XEN) gfn: 00107c00 mfn: 001aac00
(XEN) gfn: 00107e00 mfn: 001aaa00
(XEN) gfn: 00108000 mfn: 001aa800
(XEN) gfn: 00108200 mfn: 001aa600
(XEN) gfn: 00108400 mfn: 001aa400
(XEN) gfn: 00108600 mfn: 001aa200
(XEN) gfn: 00108800 mfn: 001aa000
(XEN) gfn: 00108a00 mfn: 001a9e00
(XEN) gfn: 00108c00 mfn: 001a9c00
(XEN) gfn: 00108e00 mfn: 001a9a00
(XEN) gfn: 00109000 mfn: 001a9800
(XEN) gfn: 00109200 mfn: 001a9600
(XEN) gfn: 00109400 mfn: 001a9400
(XEN) gfn: 00109600 mfn: 001a9200
(XEN) gfn: 00109800 mfn: 001a9000
(XEN) gfn: 00109a00 mfn: 001a8e00
(XEN) gfn: 00109c00 mfn: 001a8c00
(XEN) gfn: 00109e00 mfn: 001a8a00
(XEN) gfn: 0010a000 mfn: 001a8800
(XEN) gfn: 0010a200 mfn: 001a8600
(XEN) gfn: 0010a400 mfn: 001a8400
(XEN) gfn: 0010a600 mfn: 001a8200
(XEN) gfn: 0010a800 mfn: 001a8000
(XEN) gfn: 0010aa00 mfn: 001a7e00
(XEN) gfn: 0010ac00 mfn: 001a7c00
(XEN) gfn: 0010ae00 mfn: 001a7a00
(XEN) gfn: 0010b000 mfn: 001a7800
(XEN) gfn: 0010b200 mfn: 001a7600
(XEN) gfn: 0010b400 mfn: 001a7400
(XEN) gfn: 0010b600 mfn: 001a7200
(XEN) gfn: 0010b800 mfn: 001a7000
(XEN) gfn: 0010ba00 mfn: 001a6e00
(XEN) gfn: 0010bc00 mfn: 001a6c00
(XEN) gfn: 0010be00 mfn: 001a6a00
(XEN) gfn: 0010c000 mfn: 001a6800
(XEN) gfn: 0010c200 mfn: 001a6600
(XEN) gfn: 0010c400 mfn: 001a6400
(XEN) gfn: 0010c600 mfn: 001a6200
(XEN) gfn: 0010c800 mfn: 001a6000
(XEN) gfn: 0010ca00 mfn: 001a5e00
(XEN) gfn: 0010cc00 mfn: 001a5c00
(XEN) gfn: 0010ce00 mfn: 001a5a00
(XEN) gfn: 0010d000 mfn: 001a5800
(XEN) gfn: 0010d200 mfn: 001a5600
(XEN) gfn: 0010d400 mfn: 001a5400
(XEN) gfn: 0010d600 mfn: 001a5200
(XEN) gfn: 0010d800 mfn: 001a5000
(XEN) gfn: 0010da00 mfn: 001a4e00
(XEN) gfn: 0010dc00 mfn: 001a4c00
(XEN) gfn: 0010de00 mfn: 001a4a00
(XEN) gfn: 0010e000 mfn: 001a4800
(XEN) gfn: 0010e200 mfn: 001a4600
(XEN) gfn: 0010e400 mfn: 001a4400
(XEN) gfn: 0010e600 mfn: 001a4200
(XEN) gfn: 0010e800 mfn: 001a4000
(XEN) gfn: 0010ea00 mfn: 001a3e00
(XEN) gfn: 0010ec00 mfn: 001a3c00
(XEN) gfn: 0010ee00 mfn: 001a3a00
(XEN) gfn: 0010f000 mfn: 001a3800
(XEN) gfn: 0010f200 mfn: 001a3600
(XEN) gfn: 0010f400 mfn: 001a3400
(XEN) gfn: 0010f600 mfn: 001a3200
(XEN) 'A' pressed -> using alternative key handling
(XEN) stdvga.c:147:d2 entering stdvga and caching modes
+
[-- Attachment #3: Type: text/plain, Size: 126 bytes --]
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] Dump IOMMU p2m table
2012-08-15 8:54 ` Jan Beulich
2012-08-15 10:39 ` Wei Wang
@ 2012-08-16 16:27 ` Santosh Jodh
2012-08-17 9:21 ` Jan Beulich
1 sibling, 1 reply; 13+ messages in thread
From: Santosh Jodh @ 2012-08-16 16:27 UTC (permalink / raw)
To: Jan Beulich
Cc: wei.wang2@amd.com, Tim (Xen.org), xiantao.zhang@intel.com,
xen-devel
> -----Original Message-----
> From: Jan Beulich [mailto:JBeulich@suse.com]
> Sent: Wednesday, August 15, 2012 1:54 AM
> To: Santosh Jodh
> Cc: wei.wang2@amd.com; xiantao.zhang@intel.com; xen-devel; Tim
> (Xen.org)
> Subject: Re: [Xen-devel] [PATCH] Dump IOMMU p2m table
>
> >>> On 14.08.12 at 21:55, Santosh Jodh <santosh.jodh@citrix.com> wrote:
>
> Sorry to be picky; after this many rounds I would have expected that no
> further comments would be needed.
I started off trying to code to existing structure and style in individual files I was modifying. I also created IOMMU p2m dump - similar to MMU p2m dump. Over the last few days, this has evolved into cleaning up existing AMD code, indenting for more clarity etc. All good points btw.
>
> > +static void amd_dump_p2m_table_level(struct page_info* pg, int
> level,
> > + paddr_t gpa, int indent) {
> > + paddr_t address;
> > + void *table_vaddr, *pde;
> > + paddr_t next_table_maddr;
> > + int index, next_level, present;
> > + u32 *entry;
> > +
> > + if ( level < 1 )
> > + return;
> > +
> > + table_vaddr = __map_domain_page(pg);
> > + if ( table_vaddr == NULL )
> > + {
> > + printk("Failed to map IOMMU domain page %"PRIpaddr"\n",
> > + page_to_maddr(pg));
> > + return;
> > + }
> > +
> > + for ( index = 0; index < PTE_PER_TABLE_SIZE; index++ )
> > + {
> > + if ( !(index % 2) )
> > + process_pending_softirqs();
> > +
> > + pde = table_vaddr + (index * IOMMU_PAGE_TABLE_ENTRY_SIZE);
> > + next_table_maddr = amd_iommu_get_next_table_from_pte(pde);
> > + entry = (u32*)pde;
> > +
> > + present = get_field_from_reg_u32(entry[0],
> > + IOMMU_PDE_PRESENT_MASK,
> > + IOMMU_PDE_PRESENT_SHIFT);
> > +
> > + if ( !present )
> > + continue;
> > +
> > + next_level = get_field_from_reg_u32(entry[0],
> > +
> IOMMU_PDE_NEXT_LEVEL_MASK,
> > +
> > + IOMMU_PDE_NEXT_LEVEL_SHIFT);
> > +
> > + address = gpa + amd_offset_level_address(index, level);
> > + if ( next_level >= 1 )
> > + amd_dump_p2m_table_level(
> > + maddr_to_page(next_table_maddr), level - 1,
>
> Did you see Wei's cleanup patches to the code you cloned from?
> You should follow that route (replacing the ASSERT() with printing of
> the inconsistency and _not_ recursing or doing the normal printing),
> and using either "level" or "next_level"
> consistently here.
Ok - will do.
>
> > + address, indent + 1);
> > + else
> > + printk("%*s" "gfn: %08lx mfn: %08lx\n",
> > + indent, " ",
>
> printk("%*sgfn: %08lx mfn: %08lx\n",
> indent, "",
>
> I can vaguely see the point in splitting the two strings in the first
> argument, but the extra space in the third argument is definitely wrong
> - it'll make level 1 and level 2 indistinguishable.
I misunderstood how "%*s" works. That probably explains the output Wei saw.
>
> I also don't see how you addressed Wei's reporting of this still not
> printing correctly. I may be overlooking something, but without you
> making clear in the description what you changed over the previous
> version that's also relatively easy to happen.
Will add more history.
>
> > +static void vtd_dump_p2m_table_level(paddr_t pt_maddr, int level,
> paddr_t gpa,
> > + int indent) {
> > + paddr_t address;
> > + int i;
> > + struct dma_pte *pt_vaddr, *pte;
> > + int next_level;
> > +
> > + if ( level < 1 )
> > + return;
> > +
> > + pt_vaddr = map_vtd_domain_page(pt_maddr);
> > + if ( pt_vaddr == NULL )
> > + {
> > + printk("Failed to map VT-D domain page %"PRIpaddr"\n",
> pt_maddr);
> > + return;
> > + }
> > +
> > + next_level = level - 1;
> > + for ( i = 0; i < PTE_NUM; i++ )
> > + {
> > + if ( !(i % 2) )
> > + process_pending_softirqs();
> > +
> > + pte = &pt_vaddr[i];
> > + if ( !dma_pte_present(*pte) )
> > + continue;
> > +
> > + address = gpa + offset_level_address(i, level);
> > + if ( next_level >= 1 )
> > + vtd_dump_p2m_table_level(dma_pte_addr(*pte), next_level,
> > + address, indent + 1);
> > + else
> > + printk("%*s" "gfn: %08lx mfn: %08lx super=%d rd=%d
> wr=%d\n",
> > + indent, " ",
>
> Same comment as above.
Yep - got it.
>
> > + (unsigned long)(address >> PAGE_SHIFT_4K),
> > + (unsigned long)(pte->val >> PAGE_SHIFT_4K),
> > + dma_pte_superpage(*pte)? 1 : 0,
> > + dma_pte_read(*pte)? 1 : 0,
> > + dma_pte_write(*pte)? 1 : 0);
>
> Missing spaces. Even worse - given your definitions of these macros
> there's no point in using the conditional operators here at all.
>
> And, despite your claim in another response, this still isn't similar
> to AMD's variant (which still doesn't print any of these three
> attributes).
I meant structure in terms of recursion logic, level checks etc. I will just remove the extra prints to make it more similar. My original goal was to print it similar to the existing MMU p2m table.
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH] Dump IOMMU p2m table
@ 2012-08-16 16:36 Santosh Jodh
2012-08-17 9:50 ` Jan Beulich
2012-08-17 11:14 ` Wei Wang
0 siblings, 2 replies; 13+ messages in thread
From: Santosh Jodh @ 2012-08-16 16:36 UTC (permalink / raw)
To: xen-devel; +Cc: wei.wang2, tim, JBeulich, xiantao.zhang
New key handler 'o' to dump the IOMMU p2m table for each domain.
Skips dumping table for domain0.
Intel and AMD specific iommu_ops handler for dumping p2m table.
Incorporated feedback from Jan Beulich and Wei Wang.
Fixed indent printing with %*s.
Removed superflous superpage and other attribute prints.
Make next_level use consistent for AMD IOMMU dumps. Warn if found inconsistent.
Signed-off-by: Santosh Jodh<santosh.jodh@citrix.com>
diff -r 6d56e31fe1e1 -r 575a53faf4e1 xen/drivers/passthrough/amd/pci_amd_iommu.c
--- a/xen/drivers/passthrough/amd/pci_amd_iommu.c Wed Aug 15 09:41:21 2012 +0100
+++ b/xen/drivers/passthrough/amd/pci_amd_iommu.c Thu Aug 16 09:28:24 2012 -0700
@@ -22,6 +22,7 @@
#include <xen/pci.h>
#include <xen/pci_regs.h>
#include <xen/paging.h>
+#include <xen/softirq.h>
#include <asm/hvm/iommu.h>
#include <asm/amd-iommu.h>
#include <asm/hvm/svm/amd-iommu-proto.h>
@@ -512,6 +513,80 @@ static int amd_iommu_group_id(u16 seg, u
#include <asm/io_apic.h>
+static void amd_dump_p2m_table_level(struct page_info* pg, int level,
+ paddr_t gpa, int indent)
+{
+ paddr_t address;
+ void *table_vaddr, *pde;
+ paddr_t next_table_maddr;
+ int index, next_level, present;
+ u32 *entry;
+
+ if ( level < 1 )
+ return;
+
+ table_vaddr = __map_domain_page(pg);
+ if ( table_vaddr == NULL )
+ {
+ printk("Failed to map IOMMU domain page %"PRIpaddr"\n",
+ page_to_maddr(pg));
+ return;
+ }
+
+ for ( index = 0; index < PTE_PER_TABLE_SIZE; index++ )
+ {
+ if ( !(index % 2) )
+ process_pending_softirqs();
+
+ pde = table_vaddr + (index * IOMMU_PAGE_TABLE_ENTRY_SIZE);
+ next_table_maddr = amd_iommu_get_next_table_from_pte(pde);
+ entry = (u32*)pde;
+
+ present = get_field_from_reg_u32(entry[0],
+ IOMMU_PDE_PRESENT_MASK,
+ IOMMU_PDE_PRESENT_SHIFT);
+
+ if ( !present )
+ continue;
+
+ next_level = get_field_from_reg_u32(entry[0],
+ IOMMU_PDE_NEXT_LEVEL_MASK,
+ IOMMU_PDE_NEXT_LEVEL_SHIFT);
+
+ if ( next_level != (level - 1) )
+ {
+ printk("IOMMU p2m table error. next_level = %d, expected %d\n",
+ next_level, level - 1);
+
+ continue;
+ }
+
+ address = gpa + amd_offset_level_address(index, level);
+ if ( next_level >= 1 )
+ amd_dump_p2m_table_level(
+ maddr_to_page(next_table_maddr), next_level,
+ address, indent + 1);
+ else
+ printk("%*sgfn: %08lx mfn: %08lx\n",
+ indent, "",
+ (unsigned long)PFN_DOWN(address),
+ (unsigned long)PFN_DOWN(next_table_maddr));
+ }
+
+ unmap_domain_page(table_vaddr);
+}
+
+static void amd_dump_p2m_table(struct domain *d)
+{
+ struct hvm_iommu *hd = domain_hvm_iommu(d);
+
+ if ( !hd->root_table )
+ return;
+
+ printk("p2m table has %d levels\n", hd->paging_mode);
+ amd_dump_p2m_table_level(hd->root_table, hd->paging_mode, 0, 0);
+}
+
const struct iommu_ops amd_iommu_ops = {
.init = amd_iommu_domain_init,
.dom0_init = amd_iommu_dom0_init,
@@ -531,4 +606,5 @@ const struct iommu_ops amd_iommu_ops = {
.resume = amd_iommu_resume,
.share_p2m = amd_iommu_share_p2m,
.crash_shutdown = amd_iommu_suspend,
+ .dump_p2m_table = amd_dump_p2m_table,
};
diff -r 6d56e31fe1e1 -r 575a53faf4e1 xen/drivers/passthrough/iommu.c
--- a/xen/drivers/passthrough/iommu.c Wed Aug 15 09:41:21 2012 +0100
+++ b/xen/drivers/passthrough/iommu.c Thu Aug 16 09:28:24 2012 -0700
@@ -19,10 +19,12 @@
#include <xen/paging.h>
#include <xen/guest_access.h>
#include <xen/softirq.h>
+#include <xen/keyhandler.h>
#include <xsm/xsm.h>
static void parse_iommu_param(char *s);
static int iommu_populate_page_table(struct domain *d);
+static void iommu_dump_p2m_table(unsigned char key);
/*
* The 'iommu' parameter enables the IOMMU. Optional comma separated
@@ -54,6 +56,12 @@ bool_t __read_mostly amd_iommu_perdev_in
DEFINE_PER_CPU(bool_t, iommu_dont_flush_iotlb);
+static struct keyhandler iommu_p2m_table = {
+ .diagnostic = 0,
+ .u.fn = iommu_dump_p2m_table,
+ .desc = "dump iommu p2m table"
+};
+
static void __init parse_iommu_param(char *s)
{
char *ss;
@@ -119,6 +127,7 @@ void __init iommu_dom0_init(struct domai
if ( !iommu_enabled )
return;
+ register_keyhandler('o', &iommu_p2m_table);
d->need_iommu = !!iommu_dom0_strict;
if ( need_iommu(d) )
{
@@ -654,6 +663,34 @@ int iommu_do_domctl(
return ret;
}
+static void iommu_dump_p2m_table(unsigned char key)
+{
+ struct domain *d;
+ const struct iommu_ops *ops;
+
+ if ( !iommu_enabled )
+ {
+ printk("IOMMU not enabled!\n");
+ return;
+ }
+
+ ops = iommu_get_ops();
+ for_each_domain(d)
+ {
+ if ( !d->domain_id )
+ continue;
+
+ if ( iommu_use_hap_pt(d) )
+ {
+ printk("\ndomain%d IOMMU p2m table shared with MMU: \n", d->domain_id);
+ continue;
+ }
+
+ printk("\ndomain%d IOMMU p2m table: \n", d->domain_id);
+ ops->dump_p2m_table(d);
+ }
+}
+
/*
* Local variables:
* mode: C
diff -r 6d56e31fe1e1 -r 575a53faf4e1 xen/drivers/passthrough/vtd/iommu.c
--- a/xen/drivers/passthrough/vtd/iommu.c Wed Aug 15 09:41:21 2012 +0100
+++ b/xen/drivers/passthrough/vtd/iommu.c Thu Aug 16 09:28:24 2012 -0700
@@ -31,6 +31,7 @@
#include <xen/pci.h>
#include <xen/pci_regs.h>
#include <xen/keyhandler.h>
+#include <xen/softirq.h>
#include <asm/msi.h>
#include <asm/irq.h>
#if defined(__i386__) || defined(__x86_64__)
@@ -2365,6 +2366,60 @@ static void vtd_resume(void)
}
}
+static void vtd_dump_p2m_table_level(paddr_t pt_maddr, int level, paddr_t gpa,
+ int indent)
+{
+ paddr_t address;
+ int i;
+ struct dma_pte *pt_vaddr, *pte;
+ int next_level;
+
+ if ( level < 1 )
+ return;
+
+ pt_vaddr = map_vtd_domain_page(pt_maddr);
+ if ( pt_vaddr == NULL )
+ {
+ printk("Failed to map VT-D domain page %"PRIpaddr"\n", pt_maddr);
+ return;
+ }
+
+ next_level = level - 1;
+ for ( i = 0; i < PTE_NUM; i++ )
+ {
+ if ( !(i % 2) )
+ process_pending_softirqs();
+
+ pte = &pt_vaddr[i];
+ if ( !dma_pte_present(*pte) )
+ continue;
+
+ address = gpa + offset_level_address(i, level);
+ if ( next_level >= 1 )
+ vtd_dump_p2m_table_level(dma_pte_addr(*pte), next_level,
+ address, indent + 1);
+ else
+ printk("%*sgfn: %08lx mfn: %08lx\n",
+ indent, "",
+ (unsigned long)(address >> PAGE_SHIFT_4K),
+ (unsigned long)(pte->val >> PAGE_SHIFT_4K));
+ }
+
+ unmap_vtd_domain_page(pt_vaddr);
+}
+
+static void vtd_dump_p2m_table(struct domain *d)
+{
+ struct hvm_iommu *hd;
+
+ if ( list_empty(&acpi_drhd_units) )
+ return;
+
+ hd = domain_hvm_iommu(d);
+ printk("p2m table has %d levels\n", agaw_to_level(hd->agaw));
+ vtd_dump_p2m_table_level(hd->pgd_maddr, agaw_to_level(hd->agaw), 0, 0);
+}
+
const struct iommu_ops intel_iommu_ops = {
.init = intel_iommu_domain_init,
.dom0_init = intel_iommu_dom0_init,
@@ -2387,6 +2442,7 @@ const struct iommu_ops intel_iommu_ops =
.crash_shutdown = vtd_crash_shutdown,
.iotlb_flush = intel_iommu_iotlb_flush,
.iotlb_flush_all = intel_iommu_iotlb_flush_all,
+ .dump_p2m_table = vtd_dump_p2m_table,
};
/*
diff -r 6d56e31fe1e1 -r 575a53faf4e1 xen/drivers/passthrough/vtd/iommu.h
--- a/xen/drivers/passthrough/vtd/iommu.h Wed Aug 15 09:41:21 2012 +0100
+++ b/xen/drivers/passthrough/vtd/iommu.h Thu Aug 16 09:28:24 2012 -0700
@@ -248,6 +248,8 @@ struct context_entry {
#define level_to_offset_bits(l) (12 + (l - 1) * LEVEL_STRIDE)
#define address_level_offset(addr, level) \
((addr >> level_to_offset_bits(level)) & LEVEL_MASK)
+#define offset_level_address(offset, level) \
+ ((u64)(offset) << level_to_offset_bits(level))
#define level_mask(l) (((u64)(-1)) << level_to_offset_bits(l))
#define level_size(l) (1 << level_to_offset_bits(l))
#define align_to_level(addr, l) ((addr + level_size(l) - 1) & level_mask(l))
diff -r 6d56e31fe1e1 -r 575a53faf4e1 xen/include/asm-x86/hvm/svm/amd-iommu-defs.h
--- a/xen/include/asm-x86/hvm/svm/amd-iommu-defs.h Wed Aug 15 09:41:21 2012 +0100
+++ b/xen/include/asm-x86/hvm/svm/amd-iommu-defs.h Thu Aug 16 09:28:24 2012 -0700
@@ -38,6 +38,10 @@
#define PTE_PER_TABLE_ALLOC(entries) \
PAGE_SIZE * (PTE_PER_TABLE_ALIGN(entries) >> PTE_PER_TABLE_SHIFT)
+#define amd_offset_level_address(offset, level) \
+ ((u64)(offset) << (12 + (PTE_PER_TABLE_SHIFT * \
+ (level - IOMMU_PAGING_MODE_LEVEL_1))))
+
#define PCI_MIN_CAP_OFFSET 0x40
#define PCI_MAX_CAP_BLOCKS 48
#define PCI_CAP_PTR_MASK 0xFC
diff -r 6d56e31fe1e1 -r 575a53faf4e1 xen/include/xen/iommu.h
--- a/xen/include/xen/iommu.h Wed Aug 15 09:41:21 2012 +0100
+++ b/xen/include/xen/iommu.h Thu Aug 16 09:28:24 2012 -0700
@@ -141,6 +141,7 @@ struct iommu_ops {
void (*crash_shutdown)(void);
void (*iotlb_flush)(struct domain *d, unsigned long gfn, unsigned int page_count);
void (*iotlb_flush_all)(struct domain *d);
+ void (*dump_p2m_table)(struct domain *d);
};
void iommu_update_ire_from_apic(unsigned int apic, unsigned int reg, unsigned int value);
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] Dump IOMMU p2m table
2012-08-16 16:27 ` Santosh Jodh
@ 2012-08-17 9:21 ` Jan Beulich
0 siblings, 0 replies; 13+ messages in thread
From: Jan Beulich @ 2012-08-17 9:21 UTC (permalink / raw)
To: Santosh Jodh
Cc: wei.wang2@amd.com, Tim(Xen.org), xiantao.zhang@intel.com,
xen-devel
>>> On 16.08.12 at 18:27, Santosh Jodh <Santosh.Jodh@citrix.com> wrote:
>> From: Jan Beulich [mailto:JBeulich@suse.com]
>> >>> On 14.08.12 at 21:55, Santosh Jodh <santosh.jodh@citrix.com> wrote:
>> > + (unsigned long)(address >> PAGE_SHIFT_4K),
>> > + (unsigned long)(pte->val >> PAGE_SHIFT_4K),
>> > + dma_pte_superpage(*pte)? 1 : 0,
>> > + dma_pte_read(*pte)? 1 : 0,
>> > + dma_pte_write(*pte)? 1 : 0);
>>
>> Missing spaces. Even worse - given your definitions of these macros
>> there's no point in using the conditional operators here at all.
>>
>> And, despite your claim in another response, this still isn't similar
>> to AMD's variant (which still doesn't print any of these three
>> attributes).
>
> I meant structure in terms of recursion logic, level checks etc. I will just
> remove the extra prints to make it more similar. My original goal was to
> print it similar to the existing MMU p2m table.
Actually, retaining the read/write information here (and adding it
to AMD's) would be quite useful imo. The superpage part, as said
earlier, needs to be done differently anyway.
Jan
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] Dump IOMMU p2m table
2012-08-16 16:36 [PATCH] Dump IOMMU p2m table Santosh Jodh
@ 2012-08-17 9:50 ` Jan Beulich
2012-08-17 11:14 ` Wei Wang
1 sibling, 0 replies; 13+ messages in thread
From: Jan Beulich @ 2012-08-17 9:50 UTC (permalink / raw)
To: wei.wang2, Santosh Jodh, xiantao.zhang; +Cc: tim, xen-devel
>>> On 16.08.12 at 18:36, Santosh Jodh <santosh.jodh@citrix.com> wrote:
> New key handler 'o' to dump the IOMMU p2m table for each domain.
> Skips dumping table for domain0.
> Intel and AMD specific iommu_ops handler for dumping p2m table.
>
> Incorporated feedback from Jan Beulich and Wei Wang.
> Fixed indent printing with %*s.
> Removed superflous superpage and other attribute prints.
> Make next_level use consistent for AMD IOMMU dumps. Warn if found
> inconsistent.
>
> Signed-off-by: Santosh Jodh<santosh.jodh@citrix.com>
Looks okay too me now. Wei, Zhang - can we get an ack (or
more) from both of you?
Thanks, Jan
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] Dump IOMMU p2m table
2012-08-16 16:36 [PATCH] Dump IOMMU p2m table Santosh Jodh
2012-08-17 9:50 ` Jan Beulich
@ 2012-08-17 11:14 ` Wei Wang
2012-08-17 14:31 ` Santosh Jodh
1 sibling, 1 reply; 13+ messages in thread
From: Wei Wang @ 2012-08-17 11:14 UTC (permalink / raw)
To: Santosh Jodh; +Cc: xen-devel, tim, JBeulich, xiantao.zhang
On 08/16/2012 06:36 PM, Santosh Jodh wrote:
> New key handler 'o' to dump the IOMMU p2m table for each domain.
> Skips dumping table for domain0.
> Intel and AMD specific iommu_ops handler for dumping p2m table.
>
> Incorporated feedback from Jan Beulich and Wei Wang.
> Fixed indent printing with %*s.
> Removed superflous superpage and other attribute prints.
> Make next_level use consistent for AMD IOMMU dumps. Warn if found inconsistent.
>
> Signed-off-by: Santosh Jodh<santosh.jodh@citrix.com>
>
> diff -r 6d56e31fe1e1 -r 575a53faf4e1 xen/drivers/passthrough/amd/pci_amd_iommu.c
> --- a/xen/drivers/passthrough/amd/pci_amd_iommu.c Wed Aug 15 09:41:21 2012 +0100
> +++ b/xen/drivers/passthrough/amd/pci_amd_iommu.c Thu Aug 16 09:28:24 2012 -0700
> @@ -22,6 +22,7 @@
> #include<xen/pci.h>
> #include<xen/pci_regs.h>
> #include<xen/paging.h>
> +#include<xen/softirq.h>
> #include<asm/hvm/iommu.h>
> #include<asm/amd-iommu.h>
> #include<asm/hvm/svm/amd-iommu-proto.h>
> @@ -512,6 +513,80 @@ static int amd_iommu_group_id(u16 seg, u
>
> #include<asm/io_apic.h>
>
> +static void amd_dump_p2m_table_level(struct page_info* pg, int level,
> + paddr_t gpa, int indent)
> +{
> + paddr_t address;
> + void *table_vaddr, *pde;
> + paddr_t next_table_maddr;
> + int index, next_level, present;
> + u32 *entry;
> +
> + if ( level< 1 )
> + return;
> +
> + table_vaddr = __map_domain_page(pg);
> + if ( table_vaddr == NULL )
> + {
> + printk("Failed to map IOMMU domain page %"PRIpaddr"\n",
> + page_to_maddr(pg));
> + return;
> + }
> +
> + for ( index = 0; index< PTE_PER_TABLE_SIZE; index++ )
> + {
> + if ( !(index % 2) )
> + process_pending_softirqs();
> +
> + pde = table_vaddr + (index * IOMMU_PAGE_TABLE_ENTRY_SIZE);
> + next_table_maddr = amd_iommu_get_next_table_from_pte(pde);
> + entry = (u32*)pde;
> +
> + present = get_field_from_reg_u32(entry[0],
> + IOMMU_PDE_PRESENT_MASK,
> + IOMMU_PDE_PRESENT_SHIFT);
> +
> + if ( !present )
> + continue;
> +
> + next_level = get_field_from_reg_u32(entry[0],
> + IOMMU_PDE_NEXT_LEVEL_MASK,
> + IOMMU_PDE_NEXT_LEVEL_SHIFT);
> +
> + if ( next_level != (level - 1) )
> + {
> + printk("IOMMU p2m table error. next_level = %d, expected %d\n",
> + next_level, level - 1);
> +
> + continue;
> + }
HI,
This check is not proper for 2MB and 1GB pages. For example, if a guest
4 level page tables, for a 2MB entry, the next_level field will be 3
->(l4)->2(l3)->0(l2), because l2 entries becomes PTEs and PTE entries
have next_level = 0. I saw following output for those pages:
(XEN) IOMMU p2m table error. next_level = 0, expected 1
(XEN) IOMMU p2m table error. next_level = 0, expected 1
(XEN) IOMMU p2m table error. next_level = 0, expected 1
(XEN) IOMMU p2m table error. next_level = 0, expected 1
(XEN) IOMMU p2m table error. next_level = 0, expected 1
(XEN) IOMMU p2m table error. next_level = 0, expected 1
(XEN) IOMMU p2m table error. next_level = 0, expected 1
(XEN) IOMMU p2m table error. next_level = 0, expected 1
(XEN) IOMMU p2m table error. next_level = 0, expected 1
(XEN) IOMMU p2m table error. next_level = 0, expected 1
Thanks,
Wei
> +
> + address = gpa + amd_offset_level_address(index, level);
> + if ( next_level>= 1 )
> + amd_dump_p2m_table_level(
> + maddr_to_page(next_table_maddr), next_level,
> + address, indent + 1);
> + else
> + printk("%*sgfn: %08lx mfn: %08lx\n",
> + indent, "",
> + (unsigned long)PFN_DOWN(address),
> + (unsigned long)PFN_DOWN(next_table_maddr));
> + }
> +
> + unmap_domain_page(table_vaddr);
> +}
> +
> +static void amd_dump_p2m_table(struct domain *d)
> +{
> + struct hvm_iommu *hd = domain_hvm_iommu(d);
> +
> + if ( !hd->root_table )
> + return;
> +
> + printk("p2m table has %d levels\n", hd->paging_mode);
> + amd_dump_p2m_table_level(hd->root_table, hd->paging_mode, 0, 0);
> +}
> +
> const struct iommu_ops amd_iommu_ops = {
> .init = amd_iommu_domain_init,
> .dom0_init = amd_iommu_dom0_init,
> @@ -531,4 +606,5 @@ const struct iommu_ops amd_iommu_ops = {
> .resume = amd_iommu_resume,
> .share_p2m = amd_iommu_share_p2m,
> .crash_shutdown = amd_iommu_suspend,
> + .dump_p2m_table = amd_dump_p2m_table,
> };
> diff -r 6d56e31fe1e1 -r 575a53faf4e1 xen/drivers/passthrough/iommu.c
> --- a/xen/drivers/passthrough/iommu.c Wed Aug 15 09:41:21 2012 +0100
> +++ b/xen/drivers/passthrough/iommu.c Thu Aug 16 09:28:24 2012 -0700
> @@ -19,10 +19,12 @@
> #include<xen/paging.h>
> #include<xen/guest_access.h>
> #include<xen/softirq.h>
> +#include<xen/keyhandler.h>
> #include<xsm/xsm.h>
>
> static void parse_iommu_param(char *s);
> static int iommu_populate_page_table(struct domain *d);
> +static void iommu_dump_p2m_table(unsigned char key);
>
> /*
> * The 'iommu' parameter enables the IOMMU. Optional comma separated
> @@ -54,6 +56,12 @@ bool_t __read_mostly amd_iommu_perdev_in
>
> DEFINE_PER_CPU(bool_t, iommu_dont_flush_iotlb);
>
> +static struct keyhandler iommu_p2m_table = {
> + .diagnostic = 0,
> + .u.fn = iommu_dump_p2m_table,
> + .desc = "dump iommu p2m table"
> +};
> +
> static void __init parse_iommu_param(char *s)
> {
> char *ss;
> @@ -119,6 +127,7 @@ void __init iommu_dom0_init(struct domai
> if ( !iommu_enabled )
> return;
>
> + register_keyhandler('o',&iommu_p2m_table);
> d->need_iommu = !!iommu_dom0_strict;
> if ( need_iommu(d) )
> {
> @@ -654,6 +663,34 @@ int iommu_do_domctl(
> return ret;
> }
>
> +static void iommu_dump_p2m_table(unsigned char key)
> +{
> + struct domain *d;
> + const struct iommu_ops *ops;
> +
> + if ( !iommu_enabled )
> + {
> + printk("IOMMU not enabled!\n");
> + return;
> + }
> +
> + ops = iommu_get_ops();
> + for_each_domain(d)
> + {
> + if ( !d->domain_id )
> + continue;
> +
> + if ( iommu_use_hap_pt(d) )
> + {
> + printk("\ndomain%d IOMMU p2m table shared with MMU: \n", d->domain_id);
> + continue;
> + }
> +
> + printk("\ndomain%d IOMMU p2m table: \n", d->domain_id);
> + ops->dump_p2m_table(d);
> + }
> +}
> +
> /*
> * Local variables:
> * mode: C
> diff -r 6d56e31fe1e1 -r 575a53faf4e1 xen/drivers/passthrough/vtd/iommu.c
> --- a/xen/drivers/passthrough/vtd/iommu.c Wed Aug 15 09:41:21 2012 +0100
> +++ b/xen/drivers/passthrough/vtd/iommu.c Thu Aug 16 09:28:24 2012 -0700
> @@ -31,6 +31,7 @@
> #include<xen/pci.h>
> #include<xen/pci_regs.h>
> #include<xen/keyhandler.h>
> +#include<xen/softirq.h>
> #include<asm/msi.h>
> #include<asm/irq.h>
> #if defined(__i386__) || defined(__x86_64__)
> @@ -2365,6 +2366,60 @@ static void vtd_resume(void)
> }
> }
>
> +static void vtd_dump_p2m_table_level(paddr_t pt_maddr, int level, paddr_t gpa,
> + int indent)
> +{
> + paddr_t address;
> + int i;
> + struct dma_pte *pt_vaddr, *pte;
> + int next_level;
> +
> + if ( level< 1 )
> + return;
> +
> + pt_vaddr = map_vtd_domain_page(pt_maddr);
> + if ( pt_vaddr == NULL )
> + {
> + printk("Failed to map VT-D domain page %"PRIpaddr"\n", pt_maddr);
> + return;
> + }
> +
> + next_level = level - 1;
> + for ( i = 0; i< PTE_NUM; i++ )
> + {
> + if ( !(i % 2) )
> + process_pending_softirqs();
> +
> + pte =&pt_vaddr[i];
> + if ( !dma_pte_present(*pte) )
> + continue;
> +
> + address = gpa + offset_level_address(i, level);
> + if ( next_level>= 1 )
> + vtd_dump_p2m_table_level(dma_pte_addr(*pte), next_level,
> + address, indent + 1);
> + else
> + printk("%*sgfn: %08lx mfn: %08lx\n",
> + indent, "",
> + (unsigned long)(address>> PAGE_SHIFT_4K),
> + (unsigned long)(pte->val>> PAGE_SHIFT_4K));
> + }
> +
> + unmap_vtd_domain_page(pt_vaddr);
> +}
> +
> +static void vtd_dump_p2m_table(struct domain *d)
> +{
> + struct hvm_iommu *hd;
> +
> + if ( list_empty(&acpi_drhd_units) )
> + return;
> +
> + hd = domain_hvm_iommu(d);
> + printk("p2m table has %d levels\n", agaw_to_level(hd->agaw));
> + vtd_dump_p2m_table_level(hd->pgd_maddr, agaw_to_level(hd->agaw), 0, 0);
> +}
> +
> const struct iommu_ops intel_iommu_ops = {
> .init = intel_iommu_domain_init,
> .dom0_init = intel_iommu_dom0_init,
> @@ -2387,6 +2442,7 @@ const struct iommu_ops intel_iommu_ops =
> .crash_shutdown = vtd_crash_shutdown,
> .iotlb_flush = intel_iommu_iotlb_flush,
> .iotlb_flush_all = intel_iommu_iotlb_flush_all,
> + .dump_p2m_table = vtd_dump_p2m_table,
> };
>
> /*
> diff -r 6d56e31fe1e1 -r 575a53faf4e1 xen/drivers/passthrough/vtd/iommu.h
> --- a/xen/drivers/passthrough/vtd/iommu.h Wed Aug 15 09:41:21 2012 +0100
> +++ b/xen/drivers/passthrough/vtd/iommu.h Thu Aug 16 09:28:24 2012 -0700
> @@ -248,6 +248,8 @@ struct context_entry {
> #define level_to_offset_bits(l) (12 + (l - 1) * LEVEL_STRIDE)
> #define address_level_offset(addr, level) \
> ((addr>> level_to_offset_bits(level))& LEVEL_MASK)
> +#define offset_level_address(offset, level) \
> + ((u64)(offset)<< level_to_offset_bits(level))
> #define level_mask(l) (((u64)(-1))<< level_to_offset_bits(l))
> #define level_size(l) (1<< level_to_offset_bits(l))
> #define align_to_level(addr, l) ((addr + level_size(l) - 1)& level_mask(l))
> diff -r 6d56e31fe1e1 -r 575a53faf4e1 xen/include/asm-x86/hvm/svm/amd-iommu-defs.h
> --- a/xen/include/asm-x86/hvm/svm/amd-iommu-defs.h Wed Aug 15 09:41:21 2012 +0100
> +++ b/xen/include/asm-x86/hvm/svm/amd-iommu-defs.h Thu Aug 16 09:28:24 2012 -0700
> @@ -38,6 +38,10 @@
> #define PTE_PER_TABLE_ALLOC(entries) \
> PAGE_SIZE * (PTE_PER_TABLE_ALIGN(entries)>> PTE_PER_TABLE_SHIFT)
>
> +#define amd_offset_level_address(offset, level) \
> + ((u64)(offset)<< (12 + (PTE_PER_TABLE_SHIFT * \
> + (level - IOMMU_PAGING_MODE_LEVEL_1))))
> +
> #define PCI_MIN_CAP_OFFSET 0x40
> #define PCI_MAX_CAP_BLOCKS 48
> #define PCI_CAP_PTR_MASK 0xFC
> diff -r 6d56e31fe1e1 -r 575a53faf4e1 xen/include/xen/iommu.h
> --- a/xen/include/xen/iommu.h Wed Aug 15 09:41:21 2012 +0100
> +++ b/xen/include/xen/iommu.h Thu Aug 16 09:28:24 2012 -0700
> @@ -141,6 +141,7 @@ struct iommu_ops {
> void (*crash_shutdown)(void);
> void (*iotlb_flush)(struct domain *d, unsigned long gfn, unsigned int page_count);
> void (*iotlb_flush_all)(struct domain *d);
> + void (*dump_p2m_table)(struct domain *d);
> };
>
> void iommu_update_ire_from_apic(unsigned int apic, unsigned int reg, unsigned int value);
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] Dump IOMMU p2m table
2012-08-17 11:14 ` Wei Wang
@ 2012-08-17 14:31 ` Santosh Jodh
2012-08-17 14:43 ` Wei Wang
0 siblings, 1 reply; 13+ messages in thread
From: Santosh Jodh @ 2012-08-17 14:31 UTC (permalink / raw)
To: Wei Wang
Cc: xen-devel@lists.xensource.com, Tim (Xen.org), JBeulich@suse.com,
xiantao.zhang@intel.com
> -----Original Message-----
> From: Wei Wang [mailto:wei.wang2@amd.com]
> Sent: Friday, August 17, 2012 4:15 AM
> To: Santosh Jodh
> Cc: xen-devel@lists.xensource.com; xiantao.zhang@intel.com; Tim
> (Xen.org); JBeulich@suse.com
> Subject: Re: [PATCH] Dump IOMMU p2m table
>
> On 08/16/2012 06:36 PM, Santosh Jodh wrote:
> > New key handler 'o' to dump the IOMMU p2m table for each domain.
> > Skips dumping table for domain0.
> > Intel and AMD specific iommu_ops handler for dumping p2m table.
> >
> > Incorporated feedback from Jan Beulich and Wei Wang.
> > Fixed indent printing with %*s.
> > Removed superflous superpage and other attribute prints.
> > Make next_level use consistent for AMD IOMMU dumps. Warn if found
> inconsistent.
> >
> > Signed-off-by: Santosh Jodh<santosh.jodh@citrix.com>
> >
> > diff -r 6d56e31fe1e1 -r 575a53faf4e1
> xen/drivers/passthrough/amd/pci_amd_iommu.c
> > --- a/xen/drivers/passthrough/amd/pci_amd_iommu.c Wed Aug 15
> 09:41:21 2012 +0100
> > +++ b/xen/drivers/passthrough/amd/pci_amd_iommu.c Thu Aug 16
> 09:28:24 2012 -0700
> > @@ -22,6 +22,7 @@
> > #include<xen/pci.h>
> > #include<xen/pci_regs.h>
> > #include<xen/paging.h>
> > +#include<xen/softirq.h>
> > #include<asm/hvm/iommu.h>
> > #include<asm/amd-iommu.h>
> > #include<asm/hvm/svm/amd-iommu-proto.h>
> > @@ -512,6 +513,80 @@ static int amd_iommu_group_id(u16 seg, u
> >
> > #include<asm/io_apic.h>
> >
> > +static void amd_dump_p2m_table_level(struct page_info* pg, int
> level,
> > + paddr_t gpa, int indent) {
> > + paddr_t address;
> > + void *table_vaddr, *pde;
> > + paddr_t next_table_maddr;
> > + int index, next_level, present;
> > + u32 *entry;
> > +
> > + if ( level< 1 )
> > + return;
> > +
> > + table_vaddr = __map_domain_page(pg);
> > + if ( table_vaddr == NULL )
> > + {
> > + printk("Failed to map IOMMU domain page %"PRIpaddr"\n",
> > + page_to_maddr(pg));
> > + return;
> > + }
> > +
> > + for ( index = 0; index< PTE_PER_TABLE_SIZE; index++ )
> > + {
> > + if ( !(index % 2) )
> > + process_pending_softirqs();
> > +
> > + pde = table_vaddr + (index * IOMMU_PAGE_TABLE_ENTRY_SIZE);
> > + next_table_maddr = amd_iommu_get_next_table_from_pte(pde);
> > + entry = (u32*)pde;
> > +
> > + present = get_field_from_reg_u32(entry[0],
> > + IOMMU_PDE_PRESENT_MASK,
> > + IOMMU_PDE_PRESENT_SHIFT);
> > +
> > + if ( !present )
> > + continue;
> > +
> > + next_level = get_field_from_reg_u32(entry[0],
> > +
> IOMMU_PDE_NEXT_LEVEL_MASK,
> > +
> > + IOMMU_PDE_NEXT_LEVEL_SHIFT);
> > +
> > + if ( next_level != (level - 1) )
> > + {
> > + printk("IOMMU p2m table error. next_level = %d, expected
> %d\n",
> > + next_level, level - 1);
> > +
> > + continue;
> > + }
>
> HI,
>
> This check is not proper for 2MB and 1GB pages. For example, if a guest
> 4 level page tables, for a 2MB entry, the next_level field will be 3
> ->(l4)->2(l3)->0(l2), because l2 entries becomes PTEs and PTE entries
> have next_level = 0. I saw following output for those pages:
>
> (XEN) IOMMU p2m table error. next_level = 0, expected 1
> (XEN) IOMMU p2m table error. next_level = 0, expected 1
> (XEN) IOMMU p2m table error. next_level = 0, expected 1
> (XEN) IOMMU p2m table error. next_level = 0, expected 1
> (XEN) IOMMU p2m table error. next_level = 0, expected 1
> (XEN) IOMMU p2m table error. next_level = 0, expected 1
> (XEN) IOMMU p2m table error. next_level = 0, expected 1
> (XEN) IOMMU p2m table error. next_level = 0, expected 1
> (XEN) IOMMU p2m table error. next_level = 0, expected 1
> (XEN) IOMMU p2m table error. next_level = 0, expected 1
>
> Thanks,
> Wei
How about changing the check to:
if ( next_level && (next_level != (level - 1)) )
Thanks,
Santosh
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] Dump IOMMU p2m table
2012-08-17 14:31 ` Santosh Jodh
@ 2012-08-17 14:43 ` Wei Wang
0 siblings, 0 replies; 13+ messages in thread
From: Wei Wang @ 2012-08-17 14:43 UTC (permalink / raw)
To: Santosh Jodh
Cc: xen-devel@lists.xensource.com, Tim (Xen.org), JBeulich@suse.com,
xiantao.zhang@intel.com
On 08/17/2012 04:31 PM, Santosh Jodh wrote:
>
>
>> -----Original Message-----
>> From: Wei Wang [mailto:wei.wang2@amd.com]
>> Sent: Friday, August 17, 2012 4:15 AM
>> To: Santosh Jodh
>> Cc: xen-devel@lists.xensource.com; xiantao.zhang@intel.com; Tim
>> (Xen.org); JBeulich@suse.com
>> Subject: Re: [PATCH] Dump IOMMU p2m table
>>
>> On 08/16/2012 06:36 PM, Santosh Jodh wrote:
>>> New key handler 'o' to dump the IOMMU p2m table for each domain.
>>> Skips dumping table for domain0.
>>> Intel and AMD specific iommu_ops handler for dumping p2m table.
>>>
>>> Incorporated feedback from Jan Beulich and Wei Wang.
>>> Fixed indent printing with %*s.
>>> Removed superflous superpage and other attribute prints.
>>> Make next_level use consistent for AMD IOMMU dumps. Warn if found
>> inconsistent.
>>>
>>> Signed-off-by: Santosh Jodh<santosh.jodh@citrix.com>
>>>
>>> diff -r 6d56e31fe1e1 -r 575a53faf4e1
>> xen/drivers/passthrough/amd/pci_amd_iommu.c
>>> --- a/xen/drivers/passthrough/amd/pci_amd_iommu.c Wed Aug 15
>> 09:41:21 2012 +0100
>>> +++ b/xen/drivers/passthrough/amd/pci_amd_iommu.c Thu Aug 16
>> 09:28:24 2012 -0700
>>> @@ -22,6 +22,7 @@
>>> #include<xen/pci.h>
>>> #include<xen/pci_regs.h>
>>> #include<xen/paging.h>
>>> +#include<xen/softirq.h>
>>> #include<asm/hvm/iommu.h>
>>> #include<asm/amd-iommu.h>
>>> #include<asm/hvm/svm/amd-iommu-proto.h>
>>> @@ -512,6 +513,80 @@ static int amd_iommu_group_id(u16 seg, u
>>>
>>> #include<asm/io_apic.h>
>>>
>>> +static void amd_dump_p2m_table_level(struct page_info* pg, int
>> level,
>>> + paddr_t gpa, int indent) {
>>> + paddr_t address;
>>> + void *table_vaddr, *pde;
>>> + paddr_t next_table_maddr;
>>> + int index, next_level, present;
>>> + u32 *entry;
>>> +
>>> + if ( level< 1 )
>>> + return;
>>> +
>>> + table_vaddr = __map_domain_page(pg);
>>> + if ( table_vaddr == NULL )
>>> + {
>>> + printk("Failed to map IOMMU domain page %"PRIpaddr"\n",
>>> + page_to_maddr(pg));
>>> + return;
>>> + }
>>> +
>>> + for ( index = 0; index< PTE_PER_TABLE_SIZE; index++ )
>>> + {
>>> + if ( !(index % 2) )
>>> + process_pending_softirqs();
>>> +
>>> + pde = table_vaddr + (index * IOMMU_PAGE_TABLE_ENTRY_SIZE);
>>> + next_table_maddr = amd_iommu_get_next_table_from_pte(pde);
>>> + entry = (u32*)pde;
>>> +
>>> + present = get_field_from_reg_u32(entry[0],
>>> + IOMMU_PDE_PRESENT_MASK,
>>> + IOMMU_PDE_PRESENT_SHIFT);
>>> +
>>> + if ( !present )
>>> + continue;
>>> +
>>> + next_level = get_field_from_reg_u32(entry[0],
>>> +
>> IOMMU_PDE_NEXT_LEVEL_MASK,
>>> +
>>> + IOMMU_PDE_NEXT_LEVEL_SHIFT);
>>> +
>>> + if ( next_level != (level - 1) )
>>> + {
>>> + printk("IOMMU p2m table error. next_level = %d, expected
>> %d\n",
>>> + next_level, level - 1);
>>> +
>>> + continue;
>>> + }
>>
>> HI,
>>
>> This check is not proper for 2MB and 1GB pages. For example, if a guest
>> 4 level page tables, for a 2MB entry, the next_level field will be 3
>> ->(l4)->2(l3)->0(l2), because l2 entries becomes PTEs and PTE entries
>> have next_level = 0. I saw following output for those pages:
>>
>> (XEN) IOMMU p2m table error. next_level = 0, expected 1
>> (XEN) IOMMU p2m table error. next_level = 0, expected 1
>> (XEN) IOMMU p2m table error. next_level = 0, expected 1
>> (XEN) IOMMU p2m table error. next_level = 0, expected 1
>> (XEN) IOMMU p2m table error. next_level = 0, expected 1
>> (XEN) IOMMU p2m table error. next_level = 0, expected 1
>> (XEN) IOMMU p2m table error. next_level = 0, expected 1
>> (XEN) IOMMU p2m table error. next_level = 0, expected 1
>> (XEN) IOMMU p2m table error. next_level = 0, expected 1
>> (XEN) IOMMU p2m table error. next_level = 0, expected 1
>>
>> Thanks,
>> Wei
>
> How about changing the check to:
> if ( next_level&& (next_level != (level - 1)) )
That should be good, since we don't have skip levels.
Thanks,
Wei
>
> Thanks,
> Santosh
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH] Dump IOMMU p2m table
@ 2012-08-17 14:53 Santosh Jodh
0 siblings, 0 replies; 13+ messages in thread
From: Santosh Jodh @ 2012-08-17 14:53 UTC (permalink / raw)
To: xen-devel; +Cc: wei.wang2, tim, JBeulich, xiantao.zhang
New key handler 'o' to dump the IOMMU p2m table for each domain.
Skips dumping table for domain0.
Intel and AMD specific iommu_ops handler for dumping p2m table.
Incorporated feedback from Jan Beulich and Wei Wang.
Fixed indent printing with %*s.
Removed superflous superpage and other attribute prints.
Make next_level use consistent for AMD IOMMU dumps. Warn if found inconsistent.
AMD IOMMU does skip levels. Handle 2mb and 1gb IOMMU page size for AMD.
Signed-off-by: Santosh Jodh<santosh.jodh@citrix.com>
diff -r 6d56e31fe1e1 -r e26e2d1e5642 xen/drivers/passthrough/amd/pci_amd_iommu.c
--- a/xen/drivers/passthrough/amd/pci_amd_iommu.c Wed Aug 15 09:41:21 2012 +0100
+++ b/xen/drivers/passthrough/amd/pci_amd_iommu.c Fri Aug 17 07:53:38 2012 -0700
@@ -22,6 +22,7 @@
#include <xen/pci.h>
#include <xen/pci_regs.h>
#include <xen/paging.h>
+#include <xen/softirq.h>
#include <asm/hvm/iommu.h>
#include <asm/amd-iommu.h>
#include <asm/hvm/svm/amd-iommu-proto.h>
@@ -512,6 +513,80 @@ static int amd_iommu_group_id(u16 seg, u
#include <asm/io_apic.h>
+static void amd_dump_p2m_table_level(struct page_info* pg, int level,
+ paddr_t gpa, int indent)
+{
+ paddr_t address;
+ void *table_vaddr, *pde;
+ paddr_t next_table_maddr;
+ int index, next_level, present;
+ u32 *entry;
+
+ if ( level < 1 )
+ return;
+
+ table_vaddr = __map_domain_page(pg);
+ if ( table_vaddr == NULL )
+ {
+ printk("Failed to map IOMMU domain page %"PRIpaddr"\n",
+ page_to_maddr(pg));
+ return;
+ }
+
+ for ( index = 0; index < PTE_PER_TABLE_SIZE; index++ )
+ {
+ if ( !(index % 2) )
+ process_pending_softirqs();
+
+ pde = table_vaddr + (index * IOMMU_PAGE_TABLE_ENTRY_SIZE);
+ next_table_maddr = amd_iommu_get_next_table_from_pte(pde);
+ entry = (u32*)pde;
+
+ present = get_field_from_reg_u32(entry[0],
+ IOMMU_PDE_PRESENT_MASK,
+ IOMMU_PDE_PRESENT_SHIFT);
+
+ if ( !present )
+ continue;
+
+ next_level = get_field_from_reg_u32(entry[0],
+ IOMMU_PDE_NEXT_LEVEL_MASK,
+ IOMMU_PDE_NEXT_LEVEL_SHIFT);
+
+ if ( next_level && (next_level != (level - 1)) )
+ {
+ printk("IOMMU p2m table error. next_level = %d, expected %d\n",
+ next_level, level - 1);
+
+ continue;
+ }
+
+ address = gpa + amd_offset_level_address(index, level);
+ if ( next_level >= 1 )
+ amd_dump_p2m_table_level(
+ maddr_to_page(next_table_maddr), next_level,
+ address, indent + 1);
+ else
+ printk("%*sgfn: %08lx mfn: %08lx\n",
+ indent, "",
+ (unsigned long)PFN_DOWN(address),
+ (unsigned long)PFN_DOWN(next_table_maddr));
+ }
+
+ unmap_domain_page(table_vaddr);
+}
+
+static void amd_dump_p2m_table(struct domain *d)
+{
+ struct hvm_iommu *hd = domain_hvm_iommu(d);
+
+ if ( !hd->root_table )
+ return;
+
+ printk("p2m table has %d levels\n", hd->paging_mode);
+ amd_dump_p2m_table_level(hd->root_table, hd->paging_mode, 0, 0);
+}
+
const struct iommu_ops amd_iommu_ops = {
.init = amd_iommu_domain_init,
.dom0_init = amd_iommu_dom0_init,
@@ -531,4 +606,5 @@ const struct iommu_ops amd_iommu_ops = {
.resume = amd_iommu_resume,
.share_p2m = amd_iommu_share_p2m,
.crash_shutdown = amd_iommu_suspend,
+ .dump_p2m_table = amd_dump_p2m_table,
};
diff -r 6d56e31fe1e1 -r e26e2d1e5642 xen/drivers/passthrough/iommu.c
--- a/xen/drivers/passthrough/iommu.c Wed Aug 15 09:41:21 2012 +0100
+++ b/xen/drivers/passthrough/iommu.c Fri Aug 17 07:53:38 2012 -0700
@@ -19,10 +19,12 @@
#include <xen/paging.h>
#include <xen/guest_access.h>
#include <xen/softirq.h>
+#include <xen/keyhandler.h>
#include <xsm/xsm.h>
static void parse_iommu_param(char *s);
static int iommu_populate_page_table(struct domain *d);
+static void iommu_dump_p2m_table(unsigned char key);
/*
* The 'iommu' parameter enables the IOMMU. Optional comma separated
@@ -54,6 +56,12 @@ bool_t __read_mostly amd_iommu_perdev_in
DEFINE_PER_CPU(bool_t, iommu_dont_flush_iotlb);
+static struct keyhandler iommu_p2m_table = {
+ .diagnostic = 0,
+ .u.fn = iommu_dump_p2m_table,
+ .desc = "dump iommu p2m table"
+};
+
static void __init parse_iommu_param(char *s)
{
char *ss;
@@ -119,6 +127,7 @@ void __init iommu_dom0_init(struct domai
if ( !iommu_enabled )
return;
+ register_keyhandler('o', &iommu_p2m_table);
d->need_iommu = !!iommu_dom0_strict;
if ( need_iommu(d) )
{
@@ -654,6 +663,34 @@ int iommu_do_domctl(
return ret;
}
+static void iommu_dump_p2m_table(unsigned char key)
+{
+ struct domain *d;
+ const struct iommu_ops *ops;
+
+ if ( !iommu_enabled )
+ {
+ printk("IOMMU not enabled!\n");
+ return;
+ }
+
+ ops = iommu_get_ops();
+ for_each_domain(d)
+ {
+ if ( !d->domain_id )
+ continue;
+
+ if ( iommu_use_hap_pt(d) )
+ {
+ printk("\ndomain%d IOMMU p2m table shared with MMU: \n", d->domain_id);
+ continue;
+ }
+
+ printk("\ndomain%d IOMMU p2m table: \n", d->domain_id);
+ ops->dump_p2m_table(d);
+ }
+}
+
/*
* Local variables:
* mode: C
diff -r 6d56e31fe1e1 -r e26e2d1e5642 xen/drivers/passthrough/vtd/iommu.c
--- a/xen/drivers/passthrough/vtd/iommu.c Wed Aug 15 09:41:21 2012 +0100
+++ b/xen/drivers/passthrough/vtd/iommu.c Fri Aug 17 07:53:38 2012 -0700
@@ -31,6 +31,7 @@
#include <xen/pci.h>
#include <xen/pci_regs.h>
#include <xen/keyhandler.h>
+#include <xen/softirq.h>
#include <asm/msi.h>
#include <asm/irq.h>
#if defined(__i386__) || defined(__x86_64__)
@@ -2365,6 +2366,60 @@ static void vtd_resume(void)
}
}
+static void vtd_dump_p2m_table_level(paddr_t pt_maddr, int level, paddr_t gpa,
+ int indent)
+{
+ paddr_t address;
+ int i;
+ struct dma_pte *pt_vaddr, *pte;
+ int next_level;
+
+ if ( level < 1 )
+ return;
+
+ pt_vaddr = map_vtd_domain_page(pt_maddr);
+ if ( pt_vaddr == NULL )
+ {
+ printk("Failed to map VT-D domain page %"PRIpaddr"\n", pt_maddr);
+ return;
+ }
+
+ next_level = level - 1;
+ for ( i = 0; i < PTE_NUM; i++ )
+ {
+ if ( !(i % 2) )
+ process_pending_softirqs();
+
+ pte = &pt_vaddr[i];
+ if ( !dma_pte_present(*pte) )
+ continue;
+
+ address = gpa + offset_level_address(i, level);
+ if ( next_level >= 1 )
+ vtd_dump_p2m_table_level(dma_pte_addr(*pte), next_level,
+ address, indent + 1);
+ else
+ printk("%*sgfn: %08lx mfn: %08lx\n",
+ indent, "",
+ (unsigned long)(address >> PAGE_SHIFT_4K),
+ (unsigned long)(pte->val >> PAGE_SHIFT_4K));
+ }
+
+ unmap_vtd_domain_page(pt_vaddr);
+}
+
+static void vtd_dump_p2m_table(struct domain *d)
+{
+ struct hvm_iommu *hd;
+
+ if ( list_empty(&acpi_drhd_units) )
+ return;
+
+ hd = domain_hvm_iommu(d);
+ printk("p2m table has %d levels\n", agaw_to_level(hd->agaw));
+ vtd_dump_p2m_table_level(hd->pgd_maddr, agaw_to_level(hd->agaw), 0, 0);
+}
+
const struct iommu_ops intel_iommu_ops = {
.init = intel_iommu_domain_init,
.dom0_init = intel_iommu_dom0_init,
@@ -2387,6 +2442,7 @@ const struct iommu_ops intel_iommu_ops =
.crash_shutdown = vtd_crash_shutdown,
.iotlb_flush = intel_iommu_iotlb_flush,
.iotlb_flush_all = intel_iommu_iotlb_flush_all,
+ .dump_p2m_table = vtd_dump_p2m_table,
};
/*
diff -r 6d56e31fe1e1 -r e26e2d1e5642 xen/drivers/passthrough/vtd/iommu.h
--- a/xen/drivers/passthrough/vtd/iommu.h Wed Aug 15 09:41:21 2012 +0100
+++ b/xen/drivers/passthrough/vtd/iommu.h Fri Aug 17 07:53:38 2012 -0700
@@ -248,6 +248,8 @@ struct context_entry {
#define level_to_offset_bits(l) (12 + (l - 1) * LEVEL_STRIDE)
#define address_level_offset(addr, level) \
((addr >> level_to_offset_bits(level)) & LEVEL_MASK)
+#define offset_level_address(offset, level) \
+ ((u64)(offset) << level_to_offset_bits(level))
#define level_mask(l) (((u64)(-1)) << level_to_offset_bits(l))
#define level_size(l) (1 << level_to_offset_bits(l))
#define align_to_level(addr, l) ((addr + level_size(l) - 1) & level_mask(l))
diff -r 6d56e31fe1e1 -r e26e2d1e5642 xen/include/asm-x86/hvm/svm/amd-iommu-defs.h
--- a/xen/include/asm-x86/hvm/svm/amd-iommu-defs.h Wed Aug 15 09:41:21 2012 +0100
+++ b/xen/include/asm-x86/hvm/svm/amd-iommu-defs.h Fri Aug 17 07:53:38 2012 -0700
@@ -38,6 +38,10 @@
#define PTE_PER_TABLE_ALLOC(entries) \
PAGE_SIZE * (PTE_PER_TABLE_ALIGN(entries) >> PTE_PER_TABLE_SHIFT)
+#define amd_offset_level_address(offset, level) \
+ ((u64)(offset) << (12 + (PTE_PER_TABLE_SHIFT * \
+ (level - IOMMU_PAGING_MODE_LEVEL_1))))
+
#define PCI_MIN_CAP_OFFSET 0x40
#define PCI_MAX_CAP_BLOCKS 48
#define PCI_CAP_PTR_MASK 0xFC
diff -r 6d56e31fe1e1 -r e26e2d1e5642 xen/include/xen/iommu.h
--- a/xen/include/xen/iommu.h Wed Aug 15 09:41:21 2012 +0100
+++ b/xen/include/xen/iommu.h Fri Aug 17 07:53:38 2012 -0700
@@ -141,6 +141,7 @@ struct iommu_ops {
void (*crash_shutdown)(void);
void (*iotlb_flush)(struct domain *d, unsigned long gfn, unsigned int page_count);
void (*iotlb_flush_all)(struct domain *d);
+ void (*dump_p2m_table)(struct domain *d);
};
void iommu_update_ire_from_apic(unsigned int apic, unsigned int reg, unsigned int value);
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH] Dump IOMMU p2m table
@ 2012-08-17 14:57 Santosh Jodh
2012-08-21 10:04 ` Wei Wang
0 siblings, 1 reply; 13+ messages in thread
From: Santosh Jodh @ 2012-08-17 14:57 UTC (permalink / raw)
To: xen-devel; +Cc: wei.wang2, tim, JBeulich, xiantao.zhang
New key handler 'o' to dump the IOMMU p2m table for each domain.
Skips dumping table for domain0.
Intel and AMD specific iommu_ops handler for dumping p2m table.
Incorporated feedback from Jan Beulich and Wei Wang.
Fixed indent printing with %*s.
Removed superflous superpage and other attribute prints.
Make next_level use consistent for AMD IOMMU dumps. Warn if found inconsistent.
AMD IOMMU does not skip levels. Handle 2mb and 1gb IOMMU page size for AMD.
Signed-off-by: Santosh Jodh<santosh.jodh@citrix.com>
diff -r 6d56e31fe1e1 -r 995803806158 xen/drivers/passthrough/amd/pci_amd_iommu.c
--- a/xen/drivers/passthrough/amd/pci_amd_iommu.c Wed Aug 15 09:41:21 2012 +0100
+++ b/xen/drivers/passthrough/amd/pci_amd_iommu.c Fri Aug 17 07:56:55 2012 -0700
@@ -22,6 +22,7 @@
#include <xen/pci.h>
#include <xen/pci_regs.h>
#include <xen/paging.h>
+#include <xen/softirq.h>
#include <asm/hvm/iommu.h>
#include <asm/amd-iommu.h>
#include <asm/hvm/svm/amd-iommu-proto.h>
@@ -512,6 +513,80 @@ static int amd_iommu_group_id(u16 seg, u
#include <asm/io_apic.h>
+static void amd_dump_p2m_table_level(struct page_info* pg, int level,
+ paddr_t gpa, int indent)
+{
+ paddr_t address;
+ void *table_vaddr, *pde;
+ paddr_t next_table_maddr;
+ int index, next_level, present;
+ u32 *entry;
+
+ if ( level < 1 )
+ return;
+
+ table_vaddr = __map_domain_page(pg);
+ if ( table_vaddr == NULL )
+ {
+ printk("Failed to map IOMMU domain page %"PRIpaddr"\n",
+ page_to_maddr(pg));
+ return;
+ }
+
+ for ( index = 0; index < PTE_PER_TABLE_SIZE; index++ )
+ {
+ if ( !(index % 2) )
+ process_pending_softirqs();
+
+ pde = table_vaddr + (index * IOMMU_PAGE_TABLE_ENTRY_SIZE);
+ next_table_maddr = amd_iommu_get_next_table_from_pte(pde);
+ entry = (u32*)pde;
+
+ present = get_field_from_reg_u32(entry[0],
+ IOMMU_PDE_PRESENT_MASK,
+ IOMMU_PDE_PRESENT_SHIFT);
+
+ if ( !present )
+ continue;
+
+ next_level = get_field_from_reg_u32(entry[0],
+ IOMMU_PDE_NEXT_LEVEL_MASK,
+ IOMMU_PDE_NEXT_LEVEL_SHIFT);
+
+ if ( next_level && (next_level != (level - 1)) )
+ {
+ printk("IOMMU p2m table error. next_level = %d, expected %d\n",
+ next_level, level - 1);
+
+ continue;
+ }
+
+ address = gpa + amd_offset_level_address(index, level);
+ if ( next_level >= 1 )
+ amd_dump_p2m_table_level(
+ maddr_to_page(next_table_maddr), next_level,
+ address, indent + 1);
+ else
+ printk("%*sgfn: %08lx mfn: %08lx\n",
+ indent, "",
+ (unsigned long)PFN_DOWN(address),
+ (unsigned long)PFN_DOWN(next_table_maddr));
+ }
+
+ unmap_domain_page(table_vaddr);
+}
+
+static void amd_dump_p2m_table(struct domain *d)
+{
+ struct hvm_iommu *hd = domain_hvm_iommu(d);
+
+ if ( !hd->root_table )
+ return;
+
+ printk("p2m table has %d levels\n", hd->paging_mode);
+ amd_dump_p2m_table_level(hd->root_table, hd->paging_mode, 0, 0);
+}
+
const struct iommu_ops amd_iommu_ops = {
.init = amd_iommu_domain_init,
.dom0_init = amd_iommu_dom0_init,
@@ -531,4 +606,5 @@ const struct iommu_ops amd_iommu_ops = {
.resume = amd_iommu_resume,
.share_p2m = amd_iommu_share_p2m,
.crash_shutdown = amd_iommu_suspend,
+ .dump_p2m_table = amd_dump_p2m_table,
};
diff -r 6d56e31fe1e1 -r 995803806158 xen/drivers/passthrough/iommu.c
--- a/xen/drivers/passthrough/iommu.c Wed Aug 15 09:41:21 2012 +0100
+++ b/xen/drivers/passthrough/iommu.c Fri Aug 17 07:56:55 2012 -0700
@@ -19,10 +19,12 @@
#include <xen/paging.h>
#include <xen/guest_access.h>
#include <xen/softirq.h>
+#include <xen/keyhandler.h>
#include <xsm/xsm.h>
static void parse_iommu_param(char *s);
static int iommu_populate_page_table(struct domain *d);
+static void iommu_dump_p2m_table(unsigned char key);
/*
* The 'iommu' parameter enables the IOMMU. Optional comma separated
@@ -54,6 +56,12 @@ bool_t __read_mostly amd_iommu_perdev_in
DEFINE_PER_CPU(bool_t, iommu_dont_flush_iotlb);
+static struct keyhandler iommu_p2m_table = {
+ .diagnostic = 0,
+ .u.fn = iommu_dump_p2m_table,
+ .desc = "dump iommu p2m table"
+};
+
static void __init parse_iommu_param(char *s)
{
char *ss;
@@ -119,6 +127,7 @@ void __init iommu_dom0_init(struct domai
if ( !iommu_enabled )
return;
+ register_keyhandler('o', &iommu_p2m_table);
d->need_iommu = !!iommu_dom0_strict;
if ( need_iommu(d) )
{
@@ -654,6 +663,34 @@ int iommu_do_domctl(
return ret;
}
+static void iommu_dump_p2m_table(unsigned char key)
+{
+ struct domain *d;
+ const struct iommu_ops *ops;
+
+ if ( !iommu_enabled )
+ {
+ printk("IOMMU not enabled!\n");
+ return;
+ }
+
+ ops = iommu_get_ops();
+ for_each_domain(d)
+ {
+ if ( !d->domain_id )
+ continue;
+
+ if ( iommu_use_hap_pt(d) )
+ {
+ printk("\ndomain%d IOMMU p2m table shared with MMU: \n", d->domain_id);
+ continue;
+ }
+
+ printk("\ndomain%d IOMMU p2m table: \n", d->domain_id);
+ ops->dump_p2m_table(d);
+ }
+}
+
/*
* Local variables:
* mode: C
diff -r 6d56e31fe1e1 -r 995803806158 xen/drivers/passthrough/vtd/iommu.c
--- a/xen/drivers/passthrough/vtd/iommu.c Wed Aug 15 09:41:21 2012 +0100
+++ b/xen/drivers/passthrough/vtd/iommu.c Fri Aug 17 07:56:55 2012 -0700
@@ -31,6 +31,7 @@
#include <xen/pci.h>
#include <xen/pci_regs.h>
#include <xen/keyhandler.h>
+#include <xen/softirq.h>
#include <asm/msi.h>
#include <asm/irq.h>
#if defined(__i386__) || defined(__x86_64__)
@@ -2365,6 +2366,60 @@ static void vtd_resume(void)
}
}
+static void vtd_dump_p2m_table_level(paddr_t pt_maddr, int level, paddr_t gpa,
+ int indent)
+{
+ paddr_t address;
+ int i;
+ struct dma_pte *pt_vaddr, *pte;
+ int next_level;
+
+ if ( level < 1 )
+ return;
+
+ pt_vaddr = map_vtd_domain_page(pt_maddr);
+ if ( pt_vaddr == NULL )
+ {
+ printk("Failed to map VT-D domain page %"PRIpaddr"\n", pt_maddr);
+ return;
+ }
+
+ next_level = level - 1;
+ for ( i = 0; i < PTE_NUM; i++ )
+ {
+ if ( !(i % 2) )
+ process_pending_softirqs();
+
+ pte = &pt_vaddr[i];
+ if ( !dma_pte_present(*pte) )
+ continue;
+
+ address = gpa + offset_level_address(i, level);
+ if ( next_level >= 1 )
+ vtd_dump_p2m_table_level(dma_pte_addr(*pte), next_level,
+ address, indent + 1);
+ else
+ printk("%*sgfn: %08lx mfn: %08lx\n",
+ indent, "",
+ (unsigned long)(address >> PAGE_SHIFT_4K),
+ (unsigned long)(pte->val >> PAGE_SHIFT_4K));
+ }
+
+ unmap_vtd_domain_page(pt_vaddr);
+}
+
+static void vtd_dump_p2m_table(struct domain *d)
+{
+ struct hvm_iommu *hd;
+
+ if ( list_empty(&acpi_drhd_units) )
+ return;
+
+ hd = domain_hvm_iommu(d);
+ printk("p2m table has %d levels\n", agaw_to_level(hd->agaw));
+ vtd_dump_p2m_table_level(hd->pgd_maddr, agaw_to_level(hd->agaw), 0, 0);
+}
+
const struct iommu_ops intel_iommu_ops = {
.init = intel_iommu_domain_init,
.dom0_init = intel_iommu_dom0_init,
@@ -2387,6 +2442,7 @@ const struct iommu_ops intel_iommu_ops =
.crash_shutdown = vtd_crash_shutdown,
.iotlb_flush = intel_iommu_iotlb_flush,
.iotlb_flush_all = intel_iommu_iotlb_flush_all,
+ .dump_p2m_table = vtd_dump_p2m_table,
};
/*
diff -r 6d56e31fe1e1 -r 995803806158 xen/drivers/passthrough/vtd/iommu.h
--- a/xen/drivers/passthrough/vtd/iommu.h Wed Aug 15 09:41:21 2012 +0100
+++ b/xen/drivers/passthrough/vtd/iommu.h Fri Aug 17 07:56:55 2012 -0700
@@ -248,6 +248,8 @@ struct context_entry {
#define level_to_offset_bits(l) (12 + (l - 1) * LEVEL_STRIDE)
#define address_level_offset(addr, level) \
((addr >> level_to_offset_bits(level)) & LEVEL_MASK)
+#define offset_level_address(offset, level) \
+ ((u64)(offset) << level_to_offset_bits(level))
#define level_mask(l) (((u64)(-1)) << level_to_offset_bits(l))
#define level_size(l) (1 << level_to_offset_bits(l))
#define align_to_level(addr, l) ((addr + level_size(l) - 1) & level_mask(l))
diff -r 6d56e31fe1e1 -r 995803806158 xen/include/asm-x86/hvm/svm/amd-iommu-defs.h
--- a/xen/include/asm-x86/hvm/svm/amd-iommu-defs.h Wed Aug 15 09:41:21 2012 +0100
+++ b/xen/include/asm-x86/hvm/svm/amd-iommu-defs.h Fri Aug 17 07:56:55 2012 -0700
@@ -38,6 +38,10 @@
#define PTE_PER_TABLE_ALLOC(entries) \
PAGE_SIZE * (PTE_PER_TABLE_ALIGN(entries) >> PTE_PER_TABLE_SHIFT)
+#define amd_offset_level_address(offset, level) \
+ ((u64)(offset) << (12 + (PTE_PER_TABLE_SHIFT * \
+ (level - IOMMU_PAGING_MODE_LEVEL_1))))
+
#define PCI_MIN_CAP_OFFSET 0x40
#define PCI_MAX_CAP_BLOCKS 48
#define PCI_CAP_PTR_MASK 0xFC
diff -r 6d56e31fe1e1 -r 995803806158 xen/include/xen/iommu.h
--- a/xen/include/xen/iommu.h Wed Aug 15 09:41:21 2012 +0100
+++ b/xen/include/xen/iommu.h Fri Aug 17 07:56:55 2012 -0700
@@ -141,6 +141,7 @@ struct iommu_ops {
void (*crash_shutdown)(void);
void (*iotlb_flush)(struct domain *d, unsigned long gfn, unsigned int page_count);
void (*iotlb_flush_all)(struct domain *d);
+ void (*dump_p2m_table)(struct domain *d);
};
void iommu_update_ire_from_apic(unsigned int apic, unsigned int reg, unsigned int value);
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] Dump IOMMU p2m table
2012-08-17 14:57 Santosh Jodh
@ 2012-08-21 10:04 ` Wei Wang
0 siblings, 0 replies; 13+ messages in thread
From: Wei Wang @ 2012-08-21 10:04 UTC (permalink / raw)
To: Santosh Jodh; +Cc: xen-devel, tim, JBeulich, xiantao.zhang
Tested and Acked.
Thanks,
Wei
On 08/17/2012 04:57 PM, Santosh Jodh wrote:
> New key handler 'o' to dump the IOMMU p2m table for each domain.
> Skips dumping table for domain0.
> Intel and AMD specific iommu_ops handler for dumping p2m table.
>
> Incorporated feedback from Jan Beulich and Wei Wang.
> Fixed indent printing with %*s.
> Removed superflous superpage and other attribute prints.
> Make next_level use consistent for AMD IOMMU dumps. Warn if found inconsistent.
> AMD IOMMU does not skip levels. Handle 2mb and 1gb IOMMU page size for AMD.
>
> Signed-off-by: Santosh Jodh<santosh.jodh@citrix.com>
>
> diff -r 6d56e31fe1e1 -r 995803806158 xen/drivers/passthrough/amd/pci_amd_iommu.c
> --- a/xen/drivers/passthrough/amd/pci_amd_iommu.c Wed Aug 15 09:41:21 2012 +0100
> +++ b/xen/drivers/passthrough/amd/pci_amd_iommu.c Fri Aug 17 07:56:55 2012 -0700
> @@ -22,6 +22,7 @@
> #include<xen/pci.h>
> #include<xen/pci_regs.h>
> #include<xen/paging.h>
> +#include<xen/softirq.h>
> #include<asm/hvm/iommu.h>
> #include<asm/amd-iommu.h>
> #include<asm/hvm/svm/amd-iommu-proto.h>
> @@ -512,6 +513,80 @@ static int amd_iommu_group_id(u16 seg, u
>
> #include<asm/io_apic.h>
>
> +static void amd_dump_p2m_table_level(struct page_info* pg, int level,
> + paddr_t gpa, int indent)
> +{
> + paddr_t address;
> + void *table_vaddr, *pde;
> + paddr_t next_table_maddr;
> + int index, next_level, present;
> + u32 *entry;
> +
> + if ( level< 1 )
> + return;
> +
> + table_vaddr = __map_domain_page(pg);
> + if ( table_vaddr == NULL )
> + {
> + printk("Failed to map IOMMU domain page %"PRIpaddr"\n",
> + page_to_maddr(pg));
> + return;
> + }
> +
> + for ( index = 0; index< PTE_PER_TABLE_SIZE; index++ )
> + {
> + if ( !(index % 2) )
> + process_pending_softirqs();
> +
> + pde = table_vaddr + (index * IOMMU_PAGE_TABLE_ENTRY_SIZE);
> + next_table_maddr = amd_iommu_get_next_table_from_pte(pde);
> + entry = (u32*)pde;
> +
> + present = get_field_from_reg_u32(entry[0],
> + IOMMU_PDE_PRESENT_MASK,
> + IOMMU_PDE_PRESENT_SHIFT);
> +
> + if ( !present )
> + continue;
> +
> + next_level = get_field_from_reg_u32(entry[0],
> + IOMMU_PDE_NEXT_LEVEL_MASK,
> + IOMMU_PDE_NEXT_LEVEL_SHIFT);
> +
> + if ( next_level&& (next_level != (level - 1)) )
> + {
> + printk("IOMMU p2m table error. next_level = %d, expected %d\n",
> + next_level, level - 1);
> +
> + continue;
> + }
> +
> + address = gpa + amd_offset_level_address(index, level);
> + if ( next_level>= 1 )
> + amd_dump_p2m_table_level(
> + maddr_to_page(next_table_maddr), next_level,
> + address, indent + 1);
> + else
> + printk("%*sgfn: %08lx mfn: %08lx\n",
> + indent, "",
> + (unsigned long)PFN_DOWN(address),
> + (unsigned long)PFN_DOWN(next_table_maddr));
> + }
> +
> + unmap_domain_page(table_vaddr);
> +}
> +
> +static void amd_dump_p2m_table(struct domain *d)
> +{
> + struct hvm_iommu *hd = domain_hvm_iommu(d);
> +
> + if ( !hd->root_table )
> + return;
> +
> + printk("p2m table has %d levels\n", hd->paging_mode);
> + amd_dump_p2m_table_level(hd->root_table, hd->paging_mode, 0, 0);
> +}
> +
> const struct iommu_ops amd_iommu_ops = {
> .init = amd_iommu_domain_init,
> .dom0_init = amd_iommu_dom0_init,
> @@ -531,4 +606,5 @@ const struct iommu_ops amd_iommu_ops = {
> .resume = amd_iommu_resume,
> .share_p2m = amd_iommu_share_p2m,
> .crash_shutdown = amd_iommu_suspend,
> + .dump_p2m_table = amd_dump_p2m_table,
> };
> diff -r 6d56e31fe1e1 -r 995803806158 xen/drivers/passthrough/iommu.c
> --- a/xen/drivers/passthrough/iommu.c Wed Aug 15 09:41:21 2012 +0100
> +++ b/xen/drivers/passthrough/iommu.c Fri Aug 17 07:56:55 2012 -0700
> @@ -19,10 +19,12 @@
> #include<xen/paging.h>
> #include<xen/guest_access.h>
> #include<xen/softirq.h>
> +#include<xen/keyhandler.h>
> #include<xsm/xsm.h>
>
> static void parse_iommu_param(char *s);
> static int iommu_populate_page_table(struct domain *d);
> +static void iommu_dump_p2m_table(unsigned char key);
>
> /*
> * The 'iommu' parameter enables the IOMMU. Optional comma separated
> @@ -54,6 +56,12 @@ bool_t __read_mostly amd_iommu_perdev_in
>
> DEFINE_PER_CPU(bool_t, iommu_dont_flush_iotlb);
>
> +static struct keyhandler iommu_p2m_table = {
> + .diagnostic = 0,
> + .u.fn = iommu_dump_p2m_table,
> + .desc = "dump iommu p2m table"
> +};
> +
> static void __init parse_iommu_param(char *s)
> {
> char *ss;
> @@ -119,6 +127,7 @@ void __init iommu_dom0_init(struct domai
> if ( !iommu_enabled )
> return;
>
> + register_keyhandler('o',&iommu_p2m_table);
> d->need_iommu = !!iommu_dom0_strict;
> if ( need_iommu(d) )
> {
> @@ -654,6 +663,34 @@ int iommu_do_domctl(
> return ret;
> }
>
> +static void iommu_dump_p2m_table(unsigned char key)
> +{
> + struct domain *d;
> + const struct iommu_ops *ops;
> +
> + if ( !iommu_enabled )
> + {
> + printk("IOMMU not enabled!\n");
> + return;
> + }
> +
> + ops = iommu_get_ops();
> + for_each_domain(d)
> + {
> + if ( !d->domain_id )
> + continue;
> +
> + if ( iommu_use_hap_pt(d) )
> + {
> + printk("\ndomain%d IOMMU p2m table shared with MMU: \n", d->domain_id);
> + continue;
> + }
> +
> + printk("\ndomain%d IOMMU p2m table: \n", d->domain_id);
> + ops->dump_p2m_table(d);
> + }
> +}
> +
> /*
> * Local variables:
> * mode: C
> diff -r 6d56e31fe1e1 -r 995803806158 xen/drivers/passthrough/vtd/iommu.c
> --- a/xen/drivers/passthrough/vtd/iommu.c Wed Aug 15 09:41:21 2012 +0100
> +++ b/xen/drivers/passthrough/vtd/iommu.c Fri Aug 17 07:56:55 2012 -0700
> @@ -31,6 +31,7 @@
> #include<xen/pci.h>
> #include<xen/pci_regs.h>
> #include<xen/keyhandler.h>
> +#include<xen/softirq.h>
> #include<asm/msi.h>
> #include<asm/irq.h>
> #if defined(__i386__) || defined(__x86_64__)
> @@ -2365,6 +2366,60 @@ static void vtd_resume(void)
> }
> }
>
> +static void vtd_dump_p2m_table_level(paddr_t pt_maddr, int level, paddr_t gpa,
> + int indent)
> +{
> + paddr_t address;
> + int i;
> + struct dma_pte *pt_vaddr, *pte;
> + int next_level;
> +
> + if ( level< 1 )
> + return;
> +
> + pt_vaddr = map_vtd_domain_page(pt_maddr);
> + if ( pt_vaddr == NULL )
> + {
> + printk("Failed to map VT-D domain page %"PRIpaddr"\n", pt_maddr);
> + return;
> + }
> +
> + next_level = level - 1;
> + for ( i = 0; i< PTE_NUM; i++ )
> + {
> + if ( !(i % 2) )
> + process_pending_softirqs();
> +
> + pte =&pt_vaddr[i];
> + if ( !dma_pte_present(*pte) )
> + continue;
> +
> + address = gpa + offset_level_address(i, level);
> + if ( next_level>= 1 )
> + vtd_dump_p2m_table_level(dma_pte_addr(*pte), next_level,
> + address, indent + 1);
> + else
> + printk("%*sgfn: %08lx mfn: %08lx\n",
> + indent, "",
> + (unsigned long)(address>> PAGE_SHIFT_4K),
> + (unsigned long)(pte->val>> PAGE_SHIFT_4K));
> + }
> +
> + unmap_vtd_domain_page(pt_vaddr);
> +}
> +
> +static void vtd_dump_p2m_table(struct domain *d)
> +{
> + struct hvm_iommu *hd;
> +
> + if ( list_empty(&acpi_drhd_units) )
> + return;
> +
> + hd = domain_hvm_iommu(d);
> + printk("p2m table has %d levels\n", agaw_to_level(hd->agaw));
> + vtd_dump_p2m_table_level(hd->pgd_maddr, agaw_to_level(hd->agaw), 0, 0);
> +}
> +
> const struct iommu_ops intel_iommu_ops = {
> .init = intel_iommu_domain_init,
> .dom0_init = intel_iommu_dom0_init,
> @@ -2387,6 +2442,7 @@ const struct iommu_ops intel_iommu_ops =
> .crash_shutdown = vtd_crash_shutdown,
> .iotlb_flush = intel_iommu_iotlb_flush,
> .iotlb_flush_all = intel_iommu_iotlb_flush_all,
> + .dump_p2m_table = vtd_dump_p2m_table,
> };
>
> /*
> diff -r 6d56e31fe1e1 -r 995803806158 xen/drivers/passthrough/vtd/iommu.h
> --- a/xen/drivers/passthrough/vtd/iommu.h Wed Aug 15 09:41:21 2012 +0100
> +++ b/xen/drivers/passthrough/vtd/iommu.h Fri Aug 17 07:56:55 2012 -0700
> @@ -248,6 +248,8 @@ struct context_entry {
> #define level_to_offset_bits(l) (12 + (l - 1) * LEVEL_STRIDE)
> #define address_level_offset(addr, level) \
> ((addr>> level_to_offset_bits(level))& LEVEL_MASK)
> +#define offset_level_address(offset, level) \
> + ((u64)(offset)<< level_to_offset_bits(level))
> #define level_mask(l) (((u64)(-1))<< level_to_offset_bits(l))
> #define level_size(l) (1<< level_to_offset_bits(l))
> #define align_to_level(addr, l) ((addr + level_size(l) - 1)& level_mask(l))
> diff -r 6d56e31fe1e1 -r 995803806158 xen/include/asm-x86/hvm/svm/amd-iommu-defs.h
> --- a/xen/include/asm-x86/hvm/svm/amd-iommu-defs.h Wed Aug 15 09:41:21 2012 +0100
> +++ b/xen/include/asm-x86/hvm/svm/amd-iommu-defs.h Fri Aug 17 07:56:55 2012 -0700
> @@ -38,6 +38,10 @@
> #define PTE_PER_TABLE_ALLOC(entries) \
> PAGE_SIZE * (PTE_PER_TABLE_ALIGN(entries)>> PTE_PER_TABLE_SHIFT)
>
> +#define amd_offset_level_address(offset, level) \
> + ((u64)(offset)<< (12 + (PTE_PER_TABLE_SHIFT * \
> + (level - IOMMU_PAGING_MODE_LEVEL_1))))
> +
> #define PCI_MIN_CAP_OFFSET 0x40
> #define PCI_MAX_CAP_BLOCKS 48
> #define PCI_CAP_PTR_MASK 0xFC
> diff -r 6d56e31fe1e1 -r 995803806158 xen/include/xen/iommu.h
> --- a/xen/include/xen/iommu.h Wed Aug 15 09:41:21 2012 +0100
> +++ b/xen/include/xen/iommu.h Fri Aug 17 07:56:55 2012 -0700
> @@ -141,6 +141,7 @@ struct iommu_ops {
> void (*crash_shutdown)(void);
> void (*iotlb_flush)(struct domain *d, unsigned long gfn, unsigned int page_count);
> void (*iotlb_flush_all)(struct domain *d);
> + void (*dump_p2m_table)(struct domain *d);
> };
>
> void iommu_update_ire_from_apic(unsigned int apic, unsigned int reg, unsigned int value);
>
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2012-08-21 10:04 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2012-08-16 16:36 [PATCH] Dump IOMMU p2m table Santosh Jodh
2012-08-17 9:50 ` Jan Beulich
2012-08-17 11:14 ` Wei Wang
2012-08-17 14:31 ` Santosh Jodh
2012-08-17 14:43 ` Wei Wang
-- strict thread matches above, loose matches on Subject: below --
2012-08-17 14:57 Santosh Jodh
2012-08-21 10:04 ` Wei Wang
2012-08-17 14:53 Santosh Jodh
2012-08-14 19:55 Santosh Jodh
2012-08-15 8:54 ` Jan Beulich
2012-08-15 10:39 ` Wei Wang
2012-08-16 16:27 ` Santosh Jodh
2012-08-17 9:21 ` Jan Beulich
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