From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andrew Cooper Subject: Segment registers at top of stack Date: Thu, 3 Jan 2013 16:00:46 +0000 Message-ID: <50E5AB2E.7030608@citrix.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Return-path: List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Xen-devel List , Jan Beulich Cc: Tim Deegan , Keir Fraser List-Id: xen-devel@lists.xenproject.org Hello, While debugging an issue of 0xdeadbeef's appearing in a crash report, I have discovered that the es thru gs entries in cpu_user_regs appear to be completely unused on a 64bit hypervisor per-cpu stack. In 64bit mode, all segment register changes happen in {load,save}segments(). The only code I can find which ever sets these values is the NDEBUG poisoning on the VMX/SVM vmexit hypervisor entry paths. If the values are indeed completely unused, would it be sensible to remove them from the per-cpu stacks as we have now dropped support for the 32bit hypervisor (which certainly does use them)? On the plus side, it would mean that our hypervisor entry points would be at the start of a cache line, rather than half way along it, and we gain an extra 32 bytes of space on the cpu stacks. On the other hand, doing it neatly would be rather more difficult, and might just be a lot of effort for minimal gains. ~Andrew