From: Christoph Egger <chegger@amazon.de>
To: Jan Beulich <JBeulich@suse.com>
Cc: xen-devel <xen-devel@lists.xen.org>
Subject: Re: [PATCH] tools/xen-mceinj: support AMD
Date: Thu, 28 Mar 2013 15:11:42 +0100 [thread overview]
Message-ID: <51544F9E.2010504@amazon.de> (raw)
In-Reply-To: <51545A7B02000078000C94D7@nat28.tlf.novell.com>
On 28.03.13 14:58, Jan Beulich wrote:
>>>> On 28.03.13 at 14:23, Christoph Egger <chegger@amazon.de> wrote:
>> On 28.03.13 12:44, Jan Beulich wrote:
>>>>>> On 27.03.13 at 14:41, Egger Christoph <chegger@amazon.de> wrote:
>>>
>>> Didn't you also require a hypervisor side change for
>
> You didn't answer this one.
Yes, this is right for AMD but not for Intel.
I will submit it once I got the permission.
Christoph
>>>> +#define MC4_type_MISC1 0x4
>>>> +#define MC4_type_MISC2 0x5
>>>> +#define MC4_type_MISC3 0x6
>>>
>>> which also gets me back to the previously asked question why
>>> this is done only for bank 4.
>>
>> These MSRs only exist on bank 4.
>
> Sure, but it still looks pretty arbitrary. Anyway, the comment
> wasn't meant to be a NAK of any kind.
>
> Jan
>
next prev parent reply other threads:[~2013-03-28 14:11 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-03-27 13:41 [PATCH] tools/xen-mceinj: support AMD Egger Christoph
2013-03-28 11:44 ` Jan Beulich
2013-03-28 13:23 ` Christoph Egger
2013-03-28 13:58 ` Jan Beulich
2013-03-28 14:11 ` Christoph Egger [this message]
2013-04-11 7:53 ` Christoph Egger
2013-05-30 14:29 ` Christoph Egger
-- strict thread matches above, loose matches on Subject: below --
2012-10-05 14:07 Christoph Egger
2012-10-19 13:10 ` Christoph Egger
2012-10-19 14:58 ` Jan Beulich
2012-10-19 15:01 ` Ian Jackson
2012-10-19 15:05 ` Jan Beulich
2012-11-12 16:25 ` Ian Campbell
2012-11-13 1:40 ` Hao, Xudong
2012-11-13 8:40 ` Jan Beulich
2012-10-29 10:20 ` Jan Beulich
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