From: Boris Ostrovsky <boris.ostrovsky@oracle.com>
To: Dietmar Hahn <dietmar.hahn@ts.fujitsu.com>
Cc: jacob.shin@amd.com, haitao.shan@intel.com,
jun.nakajima@intel.com, suravee.suthikulpanit@amd.com,
xen-devel@lists.xen.org
Subject: Re: [PATCH 7/8] x86/VPMU: Save/restore VPMU only when necessary
Date: Wed, 10 Apr 2013 08:53:38 -0400 [thread overview]
Message-ID: <516560D2.7070000@oracle.com> (raw)
In-Reply-To: <21013935.pI9YIQR7s4@amur>
On 04/10/2013 04:57 AM, Dietmar Hahn wrote:
>
> struct vpmu_struct {
> u32 flags;
> + u32 last_pcpu;
> u32 hw_lapic_lvtpc;
> void *context;
> struct arch_vpmu_ops *arch_vpmu_ops;
> @@ -73,6 +74,8 @@ struct vpmu_struct {
> #define VPMU_PASSIVE_DOMAIN_ALLOCATED 0x8
> #define VPMU_CPU_HAS_DS 0x10 /* Has Debug Store */
> #define VPMU_CPU_HAS_BTS 0x20 /* Has Branch Trace Store */
> +#define VPMU_CONTEXT_SAVE 0x40 /* Force context save */
> +#define VPMU_STOPPED 0x80 /* Stop counters while VCPU is not running */
> Would it be better to group the VPMU_ state and context flags together and move
> special cpu flags behind?
Yes, I should do this.
I'll wait for other comments and will resend the patches.
(And will add VPMU dump code for AMD, similar to what you did for Intel.)
Thanks.
-boris
next prev parent reply other threads:[~2013-04-10 12:53 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-04-09 17:26 [PATCH 0/8] Various VPMU patches Boris Ostrovsky
2013-04-09 17:26 ` [PATCH 1/8] x86/AMD: Allow more fine-grained control of VMCB MSR Permission Map Boris Ostrovsky
2013-04-09 17:26 ` [PATCH 2/8] x86/AMD: Do not intercept access to performance counters MSRs Boris Ostrovsky
2013-04-10 13:25 ` Jan Beulich
2013-04-09 17:26 ` [PATCH 3/8] x86/AMD: Read VPMU MSRs from context when it is not loaded into HW Boris Ostrovsky
2013-04-11 18:26 ` Suravee Suthikulpanit
2013-04-11 18:34 ` Boris Ostrovsky
2013-04-11 19:30 ` Suravee Suthikulpanit
2013-04-16 15:41 ` Konrad Rzeszutek Wilk
2013-04-16 17:12 ` Jacob Shin
2013-04-16 18:36 ` Konrad Rzeszutek Wilk
2013-06-19 22:56 ` Suravee Suthikulanit
2013-06-19 23:32 ` Boris Ostrovsky
2013-06-19 23:53 ` Boris Ostrovsky
2013-04-09 17:26 ` [PATCH 4/8] x86/AMD: Stop counters on VPMU save Boris Ostrovsky
2013-04-09 17:26 ` [PATCH 5/8] x86/VPMU: Add Haswell support Boris Ostrovsky
2013-04-09 17:26 ` [PATCH 6/8] x86/VPMU: Factor out VPMU common code Boris Ostrovsky
2013-04-10 16:03 ` Nakajima, Jun
2013-04-09 17:26 ` [PATCH 7/8] x86/VPMU: Save/restore VPMU only when necessary Boris Ostrovsky
2013-04-10 8:57 ` Dietmar Hahn
2013-04-10 12:53 ` Boris Ostrovsky [this message]
2013-04-09 17:26 ` [PATCH 8/8] x86/AMD: Clean up context_update() in AMD VPMU code Boris Ostrovsky
2013-04-11 19:48 ` Suravee Suthikulpanit
2013-04-11 20:42 ` Boris Ostrovsky
2013-04-10 8:57 ` [PATCH 0/8] Various VPMU patches Dietmar Hahn
2013-04-10 18:49 ` Suravee Suthikulanit
2013-04-10 19:10 ` Boris Ostrovsky
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=516560D2.7070000@oracle.com \
--to=boris.ostrovsky@oracle.com \
--cc=dietmar.hahn@ts.fujitsu.com \
--cc=haitao.shan@intel.com \
--cc=jacob.shin@amd.com \
--cc=jun.nakajima@intel.com \
--cc=suravee.suthikulpanit@amd.com \
--cc=xen-devel@lists.xen.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).