From mboxrd@z Thu Jan 1 00:00:00 1970 From: Christoph Egger Subject: Re: [PATCH] tools/xen-mceinj: support AMD Date: Thu, 11 Apr 2013 09:53:00 +0200 Message-ID: <51666BDC.4090205@amazon.de> References: <5152F721.3050608@amazon.de> <51543B3C02000078000C937E@nat28.tlf.novell.com> <51544435.1050700@amazon.de> <51545A7B02000078000C94D7@nat28.tlf.novell.com> <51544F9E.2010504@amazon.de> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <51544F9E.2010504@amazon.de> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Jan Beulich Cc: xen-devel List-Id: xen-devel@lists.xenproject.org On 28.03.13 15:11, Christoph Egger wrote: > On 28.03.13 14:58, Jan Beulich wrote: >>>>> On 28.03.13 at 14:23, Christoph Egger wrote: >>> On 28.03.13 12:44, Jan Beulich wrote: >>>>>>> On 27.03.13 at 14:41, Egger Christoph wrote: >>>> >>>> Didn't you also require a hypervisor side change for >> >> You didn't answer this one. > > Yes, this is right for AMD but not for Intel. Jan, the patch is here: http://lists.xen.org/archives/html/xen-devel/2012-10/msg02010.html Please go ahead. Christoph > > Christoph > >>>>> +#define MC4_type_MISC1 0x4 >>>>> +#define MC4_type_MISC2 0x5 >>>>> +#define MC4_type_MISC3 0x6 >>>> >>>> which also gets me back to the previously asked question why >>>> this is done only for bank 4. >>> >>> These MSRs only exist on bank 4. >> >> Sure, but it still looks pretty arbitrary. Anyway, the comment >> wasn't meant to be a NAK of any kind. >> >> Jan >> > > > _______________________________________________ > Xen-devel mailing list > Xen-devel@lists.xen.org > http://lists.xen.org/xen-devel