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From: Boris Ostrovsky <boris.ostrovsky@oracle.com>
To: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Cc: jacob.shin@amd.com, haitao.shan@intel.com,
	jun.nakajima@intel.com, dietmar.hahn@ts.fujitsu.com,
	xen-devel@lists.xen.org
Subject: Re: [PATCH 8/8] x86/AMD: Clean up context_update() in AMD VPMU code
Date: Thu, 11 Apr 2013 16:42:34 -0400	[thread overview]
Message-ID: <5167203A.5030607@oracle.com> (raw)
In-Reply-To: <5167137D.6000300@amd.com>

On 04/11/2013 03:48 PM, Suravee Suthikulpanit wrote:
> Boris,
>
> I have a couple questions.  After patched, here is the final code:
>
> static int amd_vpmu_do_rdmsr(unsigned int msr, uint64_t *msr_content)
> {
>     struct vcpu *v = current;
>     struct vpmu_struct *vpmu = vcpu_vpmu(v);
>
>     if ( vpmu_is_set(vpmu, VPMU_STOPPED) )
>     {
>         context_load(v);
>         vpmu_reset(vpmu, VPMU_STOPPED);
>     }
>
>     if ( !vpmu_is_set(vpmu, VPMU_CONTEXT_LOADED) )
>         context_read(msr, msr_content);
>     else
>         rdmsrl(msr, *msr_content);
>
>     return 1;
> }
>
> 1. Why do you need to call context_load() here since you checking if 
> the we are in VPMU_CONTEXT_LOADED and get the appropriate copy before 
> returning the msr_content?

It is possible to be both LOADED and STOPPED. Example: guest writes 
control register (but does not enable the counters, so VPMU is not 
RUNNING). In this case amd_vpmu_load() will not get called from 
vpmu_load() so subsequent rdmsr of this control register in the guest 
will need to read from context and not from HW (since HW register is zero).

In this case context_load() really only needs to load control registers; 
the counters themselves are the same in both context and HW.

> 2. If you have already called context_load() above, shouldn't you have 
> to call "vpmu_set(vpmu, VPMU_CONTEXT_LOADED)" as well?  But then, you 
> wouldn't be needing the latter logic, isn't it?


Yes, you are right. I think we can get rid if context_read() completely 
and simply load the context if it is not LOADED or is STOPPED. Just like 
it is done in amd_vpmu_do_wrmsr().

-boris

  reply	other threads:[~2013-04-11 20:42 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-04-09 17:26 [PATCH 0/8] Various VPMU patches Boris Ostrovsky
2013-04-09 17:26 ` [PATCH 1/8] x86/AMD: Allow more fine-grained control of VMCB MSR Permission Map Boris Ostrovsky
2013-04-09 17:26 ` [PATCH 2/8] x86/AMD: Do not intercept access to performance counters MSRs Boris Ostrovsky
2013-04-10 13:25   ` Jan Beulich
2013-04-09 17:26 ` [PATCH 3/8] x86/AMD: Read VPMU MSRs from context when it is not loaded into HW Boris Ostrovsky
2013-04-11 18:26   ` Suravee Suthikulpanit
2013-04-11 18:34     ` Boris Ostrovsky
2013-04-11 19:30       ` Suravee Suthikulpanit
2013-04-16 15:41       ` Konrad Rzeszutek Wilk
2013-04-16 17:12         ` Jacob Shin
2013-04-16 18:36           ` Konrad Rzeszutek Wilk
2013-06-19 22:56             ` Suravee Suthikulanit
2013-06-19 23:32               ` Boris Ostrovsky
2013-06-19 23:53                 ` Boris Ostrovsky
2013-04-09 17:26 ` [PATCH 4/8] x86/AMD: Stop counters on VPMU save Boris Ostrovsky
2013-04-09 17:26 ` [PATCH 5/8] x86/VPMU: Add Haswell support Boris Ostrovsky
2013-04-09 17:26 ` [PATCH 6/8] x86/VPMU: Factor out VPMU common code Boris Ostrovsky
2013-04-10 16:03   ` Nakajima, Jun
2013-04-09 17:26 ` [PATCH 7/8] x86/VPMU: Save/restore VPMU only when necessary Boris Ostrovsky
2013-04-10  8:57   ` Dietmar Hahn
2013-04-10 12:53     ` Boris Ostrovsky
2013-04-09 17:26 ` [PATCH 8/8] x86/AMD: Clean up context_update() in AMD VPMU code Boris Ostrovsky
2013-04-11 19:48   ` Suravee Suthikulpanit
2013-04-11 20:42     ` Boris Ostrovsky [this message]
2013-04-10  8:57 ` [PATCH 0/8] Various VPMU patches Dietmar Hahn
2013-04-10 18:49 ` Suravee Suthikulanit
2013-04-10 19:10   ` Boris Ostrovsky

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