From mboxrd@z Thu Jan 1 00:00:00 1970 From: Christoph Egger Subject: Re: [PATCH] tools/xen-mceinj: support AMD Date: Thu, 30 May 2013 16:29:25 +0200 Message-ID: <51A76245.3060606@amazon.de> References: <5152F721.3050608@amazon.de> <51543B3C02000078000C937E@nat28.tlf.novell.com> <51544435.1050700@amazon.de> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <51544435.1050700@amazon.de> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Jan Beulich Cc: xen-devel List-Id: xen-devel@lists.xenproject.org On 28.03.13 14:23, Christoph Egger wrote: > On 28.03.13 12:44, Jan Beulich wrote: >>>>> On 27.03.13 at 14:41, Egger Christoph wrote: >> >> Didn't you also require a hypervisor side change for >> >>> +#define MC4_type_MISC1 0x4 >>> +#define MC4_type_MISC2 0x5 >>> +#define MC4_type_MISC3 0x6 >> >> which also gets me back to the previously asked question why >> this is done only for bank 4. > > These MSRs only exist on bank 4. > >>> - sprintf(path, "/local/domain/%d/memory/target", domid); >>> + snprintf(path, sizeof(path), "/local/domain/%d/memory/target", >>> domid); >> >> This continues to be valid, but unrelated. >> >>> - int type = MCE_SRAO_MEM; >>> + int type; >>> ... >>> + if (cpu_vendor == CPU_VENDOR_AMD) >>> + type = AMD_MCE_MEM; >>> + if (cpu_vendor == CPU_VENDOR_INTEL) >>> + type = INTEL_MCE_SRAO_MEM; >> >> still leaves type uninitialized for the non-Intel, non-AMD case. And >> some compilers aren't going to be able to figure out that the >> variable only gets used for either of these two cases, and will raise >> a warning. > > I haven't seen any warning but ok, will fix. I am sending a new with this fixed. Christoph