xen-devel.lists.xenproject.org archive mirror
 help / color / mirror / Atom feed
* AMD/IOMMU: revert "SR56x0 Erratum 64 - Reset all head & tail pointers"
@ 2013-06-03  7:12 Jan Beulich
  2013-06-03  9:43 ` Andrew Cooper
  0 siblings, 1 reply; 10+ messages in thread
From: Jan Beulich @ 2013-06-03  7:12 UTC (permalink / raw)
  To: xen-devel; +Cc: Andrew Cooper, suravee.suthikulpanit

[-- Attachment #1: Type: text/plain, Size: 3582 bytes --]

The code this patch added is redundant with already present code in
set_iommu_{command_buffer,{event,ppr}_log}_control(). Just switch those
ones from using writel() to writeq() for consistency.

Signed-off-by: Jan Beulich <jbeulich@suse.com>

--- a/xen/drivers/passthrough/amd/iommu_init.c
+++ b/xen/drivers/passthrough/amd/iommu_init.c
@@ -154,11 +154,6 @@ static void register_iommu_cmd_buffer_in
                          IOMMU_CMD_BUFFER_LENGTH_MASK,
                          IOMMU_CMD_BUFFER_LENGTH_SHIFT, &entry);
     writel(entry, iommu->mmio_base+IOMMU_CMD_BUFFER_BASE_HIGH_OFFSET);
-
-    /* Reset head/tail pointer. SR56x0 Erratum 64 means this might not happen
-     * automatically for us. */
-    writeq(0, iommu->mmio_base + IOMMU_CMD_BUFFER_HEAD_OFFSET);
-    writeq(0, iommu->mmio_base + IOMMU_CMD_BUFFER_TAIL_OFFSET);
 }
 
 static void register_iommu_event_log_in_mmio_space(struct amd_iommu *iommu)
@@ -187,11 +182,6 @@ static void register_iommu_event_log_in_
                         IOMMU_EVENT_LOG_LENGTH_MASK,
                         IOMMU_EVENT_LOG_LENGTH_SHIFT, &entry);
     writel(entry, iommu->mmio_base+IOMMU_EVENT_LOG_BASE_HIGH_OFFSET);
-
-    /* Reset head/tail pointer. SR56x0 Erratum 64 means this might not happen
-     * automatically for us. */
-    writeq(0, iommu->mmio_base + IOMMU_EVENT_LOG_HEAD_OFFSET);
-    writeq(0, iommu->mmio_base + IOMMU_EVENT_LOG_TAIL_OFFSET);
 }
 
 static void register_iommu_ppr_log_in_mmio_space(struct amd_iommu *iommu)
@@ -220,9 +210,6 @@ static void register_iommu_ppr_log_in_mm
                         IOMMU_PPR_LOG_LENGTH_MASK,
                         IOMMU_PPR_LOG_LENGTH_SHIFT, &entry);
     writel(entry, iommu->mmio_base + IOMMU_PPR_LOG_BASE_HIGH_OFFSET);
-
-    writeq(0, iommu->mmio_base + IOMMU_PPR_LOG_HEAD_OFFSET);
-    writeq(0, iommu->mmio_base + IOMMU_PPR_LOG_TAIL_OFFSET);
 }
 
 
@@ -267,8 +254,8 @@ static void set_iommu_command_buffer_con
     /*reset head and tail pointer manually before enablement */
     if ( enable )
     {
-        writel(0x0, iommu->mmio_base + IOMMU_CMD_BUFFER_HEAD_OFFSET);
-        writel(0x0, iommu->mmio_base + IOMMU_CMD_BUFFER_TAIL_OFFSET);
+        writeq(0, iommu->mmio_base + IOMMU_CMD_BUFFER_HEAD_OFFSET);
+        writeq(0, iommu->mmio_base + IOMMU_CMD_BUFFER_TAIL_OFFSET);
 
         iommu_set_bit(&entry, IOMMU_CONTROL_COMMAND_BUFFER_ENABLE_SHIFT);
     }
@@ -326,8 +313,8 @@ static void set_iommu_event_log_control(
     /*reset head and tail pointer manually before enablement */
     if ( enable )
     {
-        writel(0x0, iommu->mmio_base + IOMMU_EVENT_LOG_HEAD_OFFSET);
-        writel(0x0, iommu->mmio_base + IOMMU_EVENT_LOG_TAIL_OFFSET);
+        writeq(0, iommu->mmio_base + IOMMU_EVENT_LOG_HEAD_OFFSET);
+        writeq(0, iommu->mmio_base + IOMMU_EVENT_LOG_TAIL_OFFSET);
 
         iommu_set_bit(&entry, IOMMU_CONTROL_EVENT_LOG_INT_SHIFT);
         iommu_set_bit(&entry, IOMMU_CONTROL_EVENT_LOG_ENABLE_SHIFT);
@@ -353,8 +340,8 @@ static void set_iommu_ppr_log_control(st
     /*reset head and tail pointer manually before enablement */
     if ( enable )
     {
-        writel(0x0, iommu->mmio_base + IOMMU_PPR_LOG_HEAD_OFFSET);
-        writel(0x0, iommu->mmio_base + IOMMU_PPR_LOG_TAIL_OFFSET);
+        writeq(0, iommu->mmio_base + IOMMU_PPR_LOG_HEAD_OFFSET);
+        writeq(0, iommu->mmio_base + IOMMU_PPR_LOG_TAIL_OFFSET);
 
         iommu_set_bit(&entry, IOMMU_CONTROL_PPR_ENABLE_SHIFT);
         iommu_set_bit(&entry, IOMMU_CONTROL_PPR_INT_SHIFT);




[-- Attachment #2: AMD-IOMMU-erratum-64-revert.patch --]
[-- Type: text/plain, Size: 3650 bytes --]

AMD/IOMMU: revert "SR56x0 Erratum 64 - Reset all head & tail pointers"

The code this patch added is redundant with already present code in
set_iommu_{command_buffer,{event,ppr}_log}_control(). Just switch those
ones from using writel() to writeq() for consistency.

Signed-off-by: Jan Beulich <jbeulich@suse.com>

--- a/xen/drivers/passthrough/amd/iommu_init.c
+++ b/xen/drivers/passthrough/amd/iommu_init.c
@@ -154,11 +154,6 @@ static void register_iommu_cmd_buffer_in
                          IOMMU_CMD_BUFFER_LENGTH_MASK,
                          IOMMU_CMD_BUFFER_LENGTH_SHIFT, &entry);
     writel(entry, iommu->mmio_base+IOMMU_CMD_BUFFER_BASE_HIGH_OFFSET);
-
-    /* Reset head/tail pointer. SR56x0 Erratum 64 means this might not happen
-     * automatically for us. */
-    writeq(0, iommu->mmio_base + IOMMU_CMD_BUFFER_HEAD_OFFSET);
-    writeq(0, iommu->mmio_base + IOMMU_CMD_BUFFER_TAIL_OFFSET);
 }
 
 static void register_iommu_event_log_in_mmio_space(struct amd_iommu *iommu)
@@ -187,11 +182,6 @@ static void register_iommu_event_log_in_
                         IOMMU_EVENT_LOG_LENGTH_MASK,
                         IOMMU_EVENT_LOG_LENGTH_SHIFT, &entry);
     writel(entry, iommu->mmio_base+IOMMU_EVENT_LOG_BASE_HIGH_OFFSET);
-
-    /* Reset head/tail pointer. SR56x0 Erratum 64 means this might not happen
-     * automatically for us. */
-    writeq(0, iommu->mmio_base + IOMMU_EVENT_LOG_HEAD_OFFSET);
-    writeq(0, iommu->mmio_base + IOMMU_EVENT_LOG_TAIL_OFFSET);
 }
 
 static void register_iommu_ppr_log_in_mmio_space(struct amd_iommu *iommu)
@@ -220,9 +210,6 @@ static void register_iommu_ppr_log_in_mm
                         IOMMU_PPR_LOG_LENGTH_MASK,
                         IOMMU_PPR_LOG_LENGTH_SHIFT, &entry);
     writel(entry, iommu->mmio_base + IOMMU_PPR_LOG_BASE_HIGH_OFFSET);
-
-    writeq(0, iommu->mmio_base + IOMMU_PPR_LOG_HEAD_OFFSET);
-    writeq(0, iommu->mmio_base + IOMMU_PPR_LOG_TAIL_OFFSET);
 }
 
 
@@ -267,8 +254,8 @@ static void set_iommu_command_buffer_con
     /*reset head and tail pointer manually before enablement */
     if ( enable )
     {
-        writel(0x0, iommu->mmio_base + IOMMU_CMD_BUFFER_HEAD_OFFSET);
-        writel(0x0, iommu->mmio_base + IOMMU_CMD_BUFFER_TAIL_OFFSET);
+        writeq(0, iommu->mmio_base + IOMMU_CMD_BUFFER_HEAD_OFFSET);
+        writeq(0, iommu->mmio_base + IOMMU_CMD_BUFFER_TAIL_OFFSET);
 
         iommu_set_bit(&entry, IOMMU_CONTROL_COMMAND_BUFFER_ENABLE_SHIFT);
     }
@@ -326,8 +313,8 @@ static void set_iommu_event_log_control(
     /*reset head and tail pointer manually before enablement */
     if ( enable )
     {
-        writel(0x0, iommu->mmio_base + IOMMU_EVENT_LOG_HEAD_OFFSET);
-        writel(0x0, iommu->mmio_base + IOMMU_EVENT_LOG_TAIL_OFFSET);
+        writeq(0, iommu->mmio_base + IOMMU_EVENT_LOG_HEAD_OFFSET);
+        writeq(0, iommu->mmio_base + IOMMU_EVENT_LOG_TAIL_OFFSET);
 
         iommu_set_bit(&entry, IOMMU_CONTROL_EVENT_LOG_INT_SHIFT);
         iommu_set_bit(&entry, IOMMU_CONTROL_EVENT_LOG_ENABLE_SHIFT);
@@ -353,8 +340,8 @@ static void set_iommu_ppr_log_control(st
     /*reset head and tail pointer manually before enablement */
     if ( enable )
     {
-        writel(0x0, iommu->mmio_base + IOMMU_PPR_LOG_HEAD_OFFSET);
-        writel(0x0, iommu->mmio_base + IOMMU_PPR_LOG_TAIL_OFFSET);
+        writeq(0, iommu->mmio_base + IOMMU_PPR_LOG_HEAD_OFFSET);
+        writeq(0, iommu->mmio_base + IOMMU_PPR_LOG_TAIL_OFFSET);
 
         iommu_set_bit(&entry, IOMMU_CONTROL_PPR_ENABLE_SHIFT);
         iommu_set_bit(&entry, IOMMU_CONTROL_PPR_INT_SHIFT);

[-- Attachment #3: Type: text/plain, Size: 126 bytes --]

_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
http://lists.xen.org/xen-devel

^ permalink raw reply	[flat|nested] 10+ messages in thread

end of thread, other threads:[~2013-06-05  6:53 UTC | newest]

Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2013-06-03  7:12 AMD/IOMMU: revert "SR56x0 Erratum 64 - Reset all head & tail pointers" Jan Beulich
2013-06-03  9:43 ` Andrew Cooper
2013-06-04  4:41   ` Suravee Suthikulpanit
2013-06-04  6:33     ` Jan Beulich
2013-06-05  6:53       ` Suravee Suthikulpanit
2013-06-04  9:24   ` George Dunlap
2013-06-04  9:30     ` Andrew Cooper
2013-06-04  9:38       ` George Dunlap
2013-06-04  9:53         ` Ian Campbell
2013-06-04  9:56           ` George Dunlap

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).