From mboxrd@z Thu Jan 1 00:00:00 1970 From: Julien Grall Subject: Re: [PATCH v2 2/2] xen/arm32: implement VFP context switch Date: Mon, 03 Jun 2013 12:10:08 +0100 Message-ID: <51AC7990.4020400@linaro.org> References: <1369929719-26298-1-git-send-email-julien.grall@linaro.org> <1369929719-26298-3-git-send-email-julien.grall@linaro.org> <1370009536.5199.171.camel@zakaz.uk.xensource.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1370009536.5199.171.camel@zakaz.uk.xensource.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Ian Campbell Cc: Stefano.Stabellini@eu.citrix.com, tim@xen.org, patches@linaro.org, xen-devel@lists.xen.org List-Id: xen-devel@lists.xenproject.org On 05/31/2013 03:12 PM, Ian Campbell wrote: > On Thu, 2013-05-30 at 17:01 +0100, Julien Grall wrote: >> +void vfp_save_state(struct vcpu *v) >> +{ >> + uint32_t tmp; >> + >> + v->arch.vfp.fpexc = READ_CP32(FPEXC); > > The docs seem to call for reading this via an explicit VMRS > instruction. > > Looking at the ARM ARM this seems to be an alias for the encoding of an > MRC instruction corresponding to reading FPEXC as you have done. Did you > have a reference for that aliasing? (I'm not finding it in the ARM ARM). > > Are you avoiding the mnemonic to avoid issues with binutils providing > the instruction? > >> + >> + WRITE_CP32(v->arch.vfp.fpexc | FPEXC_EN, FPEXC); > > This being a CP write, do we need an isb? Will this write complete > before the following read from FPSCR otherwise? In fact, isb seems to be unnecessary: "Writes to the FPEXC can have side-effects on various aspects of processor operation. All of these side-effects are synchronous to the FPEXC write. This means they are guaranteed not to be visible to earlier instructions in the execution stream, and they are guaranteed to be visible to later instructions in the execution stream." -- Julien