From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
To: Andrew Cooper <andrew.cooper3@citrix.com>
Cc: Jan Beulich <JBeulich@suse.com>, xen-devel <xen-devel@lists.xen.org>
Subject: Re: AMD/IOMMU: revert "SR56x0 Erratum 64 - Reset all head & tail pointers"
Date: Mon, 3 Jun 2013 23:41:15 -0500 [thread overview]
Message-ID: <51AD6FEB.2000801@amd.com> (raw)
In-Reply-To: <51AC6540.9070101@citrix.com>
Sorry, I also missed that :(
Suravee
On 6/3/2013 4:43 AM, Andrew Cooper wrote:
> On 03/06/13 08:12, Jan Beulich wrote:
>> The code this patch added is redundant with already present code in
>> set_iommu_{command_buffer,{event,ppr}_log}_control(). Just switch those
>> ones from using writel() to writeq() for consistency.
>>
>> Signed-off-by: Jan Beulich <jbeulich@suse.com>
> Yikes - I clearly didn't do a good job looking to see whether this issue
> had already been addressed.
>
> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
>
>> --- a/xen/drivers/passthrough/amd/iommu_init.c
>> +++ b/xen/drivers/passthrough/amd/iommu_init.c
>> @@ -154,11 +154,6 @@ static void register_iommu_cmd_buffer_in
>> IOMMU_CMD_BUFFER_LENGTH_MASK,
>> IOMMU_CMD_BUFFER_LENGTH_SHIFT, &entry);
>> writel(entry, iommu->mmio_base+IOMMU_CMD_BUFFER_BASE_HIGH_OFFSET);
>> -
>> - /* Reset head/tail pointer. SR56x0 Erratum 64 means this might not happen
>> - * automatically for us. */
>> - writeq(0, iommu->mmio_base + IOMMU_CMD_BUFFER_HEAD_OFFSET);
>> - writeq(0, iommu->mmio_base + IOMMU_CMD_BUFFER_TAIL_OFFSET);
>> }
>>
>> static void register_iommu_event_log_in_mmio_space(struct amd_iommu *iommu)
>> @@ -187,11 +182,6 @@ static void register_iommu_event_log_in_
>> IOMMU_EVENT_LOG_LENGTH_MASK,
>> IOMMU_EVENT_LOG_LENGTH_SHIFT, &entry);
>> writel(entry, iommu->mmio_base+IOMMU_EVENT_LOG_BASE_HIGH_OFFSET);
>> -
>> - /* Reset head/tail pointer. SR56x0 Erratum 64 means this might not happen
>> - * automatically for us. */
>> - writeq(0, iommu->mmio_base + IOMMU_EVENT_LOG_HEAD_OFFSET);
>> - writeq(0, iommu->mmio_base + IOMMU_EVENT_LOG_TAIL_OFFSET);
>> }
>>
>> static void register_iommu_ppr_log_in_mmio_space(struct amd_iommu *iommu)
>> @@ -220,9 +210,6 @@ static void register_iommu_ppr_log_in_mm
>> IOMMU_PPR_LOG_LENGTH_MASK,
>> IOMMU_PPR_LOG_LENGTH_SHIFT, &entry);
>> writel(entry, iommu->mmio_base + IOMMU_PPR_LOG_BASE_HIGH_OFFSET);
>> -
>> - writeq(0, iommu->mmio_base + IOMMU_PPR_LOG_HEAD_OFFSET);
>> - writeq(0, iommu->mmio_base + IOMMU_PPR_LOG_TAIL_OFFSET);
>> }
>>
>>
>> @@ -267,8 +254,8 @@ static void set_iommu_command_buffer_con
>> /*reset head and tail pointer manually before enablement */
>> if ( enable )
>> {
>> - writel(0x0, iommu->mmio_base + IOMMU_CMD_BUFFER_HEAD_OFFSET);
>> - writel(0x0, iommu->mmio_base + IOMMU_CMD_BUFFER_TAIL_OFFSET);
>> + writeq(0, iommu->mmio_base + IOMMU_CMD_BUFFER_HEAD_OFFSET);
>> + writeq(0, iommu->mmio_base + IOMMU_CMD_BUFFER_TAIL_OFFSET);
>>
>> iommu_set_bit(&entry, IOMMU_CONTROL_COMMAND_BUFFER_ENABLE_SHIFT);
>> }
>> @@ -326,8 +313,8 @@ static void set_iommu_event_log_control(
>> /*reset head and tail pointer manually before enablement */
>> if ( enable )
>> {
>> - writel(0x0, iommu->mmio_base + IOMMU_EVENT_LOG_HEAD_OFFSET);
>> - writel(0x0, iommu->mmio_base + IOMMU_EVENT_LOG_TAIL_OFFSET);
>> + writeq(0, iommu->mmio_base + IOMMU_EVENT_LOG_HEAD_OFFSET);
>> + writeq(0, iommu->mmio_base + IOMMU_EVENT_LOG_TAIL_OFFSET);
>>
>> iommu_set_bit(&entry, IOMMU_CONTROL_EVENT_LOG_INT_SHIFT);
>> iommu_set_bit(&entry, IOMMU_CONTROL_EVENT_LOG_ENABLE_SHIFT);
>> @@ -353,8 +340,8 @@ static void set_iommu_ppr_log_control(st
>> /*reset head and tail pointer manually before enablement */
>> if ( enable )
>> {
>> - writel(0x0, iommu->mmio_base + IOMMU_PPR_LOG_HEAD_OFFSET);
>> - writel(0x0, iommu->mmio_base + IOMMU_PPR_LOG_TAIL_OFFSET);
>> + writeq(0, iommu->mmio_base + IOMMU_PPR_LOG_HEAD_OFFSET);
>> + writeq(0, iommu->mmio_base + IOMMU_PPR_LOG_TAIL_OFFSET);
>>
>> iommu_set_bit(&entry, IOMMU_CONTROL_PPR_ENABLE_SHIFT);
>> iommu_set_bit(&entry, IOMMU_CONTROL_PPR_INT_SHIFT);
>>
>>
>>
>
next prev parent reply other threads:[~2013-06-04 4:41 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-06-03 7:12 AMD/IOMMU: revert "SR56x0 Erratum 64 - Reset all head & tail pointers" Jan Beulich
2013-06-03 9:43 ` Andrew Cooper
2013-06-04 4:41 ` Suravee Suthikulpanit [this message]
2013-06-04 6:33 ` Jan Beulich
2013-06-05 6:53 ` Suravee Suthikulpanit
2013-06-04 9:24 ` George Dunlap
2013-06-04 9:30 ` Andrew Cooper
2013-06-04 9:38 ` George Dunlap
2013-06-04 9:53 ` Ian Campbell
2013-06-04 9:56 ` George Dunlap
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=51AD6FEB.2000801@amd.com \
--to=suravee.suthikulpanit@amd.com \
--cc=JBeulich@suse.com \
--cc=andrew.cooper3@citrix.com \
--cc=xen-devel@lists.xen.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).