From mboxrd@z Thu Jan  1 00:00:00 1970
From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Subject: Re: AMD/IOMMU: revert "SR56x0 Erratum 64 - Reset all
 head & tail pointers"
Date: Mon, 3 Jun 2013 23:41:15 -0500
Message-ID: <51AD6FEB.2000801@amd.com>
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	<51AC6540.9070101@citrix.com>
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To: Andrew Cooper <andrew.cooper3@citrix.com>
Cc: Jan Beulich <JBeulich@suse.com>, xen-devel <xen-devel@lists.xen.org>
List-Id: xen-devel@lists.xenproject.org

Sorry, I also missed that :(

Suravee

On 6/3/2013 4:43 AM, Andrew Cooper wrote:
> On 03/06/13 08:12, Jan Beulich wrote:
>> The code this patch added is redundant with already present code in
>> set_iommu_{command_buffer,{event,ppr}_log}_control(). Just switch those
>> ones from using writel() to writeq() for consistency.
>>
>> Signed-off-by: Jan Beulich <jbeulich@suse.com>
> Yikes - I clearly didn't do a good job looking to see whether this issue
> had already been addressed.
>
> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
>
>> --- a/xen/drivers/passthrough/amd/iommu_init.c
>> +++ b/xen/drivers/passthrough/amd/iommu_init.c
>> @@ -154,11 +154,6 @@ static void register_iommu_cmd_buffer_in
>>                            IOMMU_CMD_BUFFER_LENGTH_MASK,
>>                            IOMMU_CMD_BUFFER_LENGTH_SHIFT, &entry);
>>       writel(entry, iommu->mmio_base+IOMMU_CMD_BUFFER_BASE_HIGH_OFFSET);
>> -
>> -    /* Reset head/tail pointer. SR56x0 Erratum 64 means this might not happen
>> -     * automatically for us. */
>> -    writeq(0, iommu->mmio_base + IOMMU_CMD_BUFFER_HEAD_OFFSET);
>> -    writeq(0, iommu->mmio_base + IOMMU_CMD_BUFFER_TAIL_OFFSET);
>>   }
>>   
>>   static void register_iommu_event_log_in_mmio_space(struct amd_iommu *iommu)
>> @@ -187,11 +182,6 @@ static void register_iommu_event_log_in_
>>                           IOMMU_EVENT_LOG_LENGTH_MASK,
>>                           IOMMU_EVENT_LOG_LENGTH_SHIFT, &entry);
>>       writel(entry, iommu->mmio_base+IOMMU_EVENT_LOG_BASE_HIGH_OFFSET);
>> -
>> -    /* Reset head/tail pointer. SR56x0 Erratum 64 means this might not happen
>> -     * automatically for us. */
>> -    writeq(0, iommu->mmio_base + IOMMU_EVENT_LOG_HEAD_OFFSET);
>> -    writeq(0, iommu->mmio_base + IOMMU_EVENT_LOG_TAIL_OFFSET);
>>   }
>>   
>>   static void register_iommu_ppr_log_in_mmio_space(struct amd_iommu *iommu)
>> @@ -220,9 +210,6 @@ static void register_iommu_ppr_log_in_mm
>>                           IOMMU_PPR_LOG_LENGTH_MASK,
>>                           IOMMU_PPR_LOG_LENGTH_SHIFT, &entry);
>>       writel(entry, iommu->mmio_base + IOMMU_PPR_LOG_BASE_HIGH_OFFSET);
>> -
>> -    writeq(0, iommu->mmio_base + IOMMU_PPR_LOG_HEAD_OFFSET);
>> -    writeq(0, iommu->mmio_base + IOMMU_PPR_LOG_TAIL_OFFSET);
>>   }
>>   
>>   
>> @@ -267,8 +254,8 @@ static void set_iommu_command_buffer_con
>>       /*reset head and tail pointer manually before enablement */
>>       if ( enable )
>>       {
>> -        writel(0x0, iommu->mmio_base + IOMMU_CMD_BUFFER_HEAD_OFFSET);
>> -        writel(0x0, iommu->mmio_base + IOMMU_CMD_BUFFER_TAIL_OFFSET);
>> +        writeq(0, iommu->mmio_base + IOMMU_CMD_BUFFER_HEAD_OFFSET);
>> +        writeq(0, iommu->mmio_base + IOMMU_CMD_BUFFER_TAIL_OFFSET);
>>   
>>           iommu_set_bit(&entry, IOMMU_CONTROL_COMMAND_BUFFER_ENABLE_SHIFT);
>>       }
>> @@ -326,8 +313,8 @@ static void set_iommu_event_log_control(
>>       /*reset head and tail pointer manually before enablement */
>>       if ( enable )
>>       {
>> -        writel(0x0, iommu->mmio_base + IOMMU_EVENT_LOG_HEAD_OFFSET);
>> -        writel(0x0, iommu->mmio_base + IOMMU_EVENT_LOG_TAIL_OFFSET);
>> +        writeq(0, iommu->mmio_base + IOMMU_EVENT_LOG_HEAD_OFFSET);
>> +        writeq(0, iommu->mmio_base + IOMMU_EVENT_LOG_TAIL_OFFSET);
>>   
>>           iommu_set_bit(&entry, IOMMU_CONTROL_EVENT_LOG_INT_SHIFT);
>>           iommu_set_bit(&entry, IOMMU_CONTROL_EVENT_LOG_ENABLE_SHIFT);
>> @@ -353,8 +340,8 @@ static void set_iommu_ppr_log_control(st
>>       /*reset head and tail pointer manually before enablement */
>>       if ( enable )
>>       {
>> -        writel(0x0, iommu->mmio_base + IOMMU_PPR_LOG_HEAD_OFFSET);
>> -        writel(0x0, iommu->mmio_base + IOMMU_PPR_LOG_TAIL_OFFSET);
>> +        writeq(0, iommu->mmio_base + IOMMU_PPR_LOG_HEAD_OFFSET);
>> +        writeq(0, iommu->mmio_base + IOMMU_PPR_LOG_TAIL_OFFSET);
>>   
>>           iommu_set_bit(&entry, IOMMU_CONTROL_PPR_ENABLE_SHIFT);
>>           iommu_set_bit(&entry, IOMMU_CONTROL_PPR_INT_SHIFT);
>>
>>
>>
>