From mboxrd@z Thu Jan 1 00:00:00 1970 From: Suravee Suthikulanit Subject: Re: [PATCH 1/2 v3] iommu/amd: Fix logic for clearing the IOMMU interrupt bits Date: Mon, 10 Jun 2013 08:58:41 -0500 Message-ID: <51B5DB91.2070200@amd.com> References: <1370840751-11277-1-git-send-email-suravee.suthikulpanit@amd.com> <51B5CCF002000078000DC9A5@nat28.tlf.novell.com> <20130610121855.GE8802@ocelot.phlegethon.org> <51B5E33802000078000DCA72@nat28.tlf.novell.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <51B5E33802000078000DCA72@nat28.tlf.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Jan Beulich Cc: Tim Deegan , xen-devel@lists.xen.org List-Id: xen-devel@lists.xenproject.org On 6/10/2013 7:31 AM, Jan Beulich wrote: >>> @@ -439,8 +439,8 @@ static void iommu_reset_log(struct amd_i >>> >> >>> >> ctrl_func(iommu, IOMMU_CONTROL_DISABLED); >>> >> >>> >>- /*clear overflow bit */ >>> >>- iommu_clear_bit(&entry, of_bit); >>> >>+ /* RW1C overflow bit */ >>> >>+ iommu_set_bit(&entry, of_bit); >>> >> writel(entry, iommu->mmio_base + IOMMU_STATUS_MMIO_OFFSET); >> > >> >Won't this clear all other status bits as well? > Yes it will, albeit not because of this patch. But I guess we should > fix this as we go. Expect v4 soon... Sorry, I missed one case. Suravee