From mboxrd@z Thu Jan 1 00:00:00 1970 From: Suravee Suthikulanit Subject: Re: [PATCH 1/2 v5] iommu/amd: Fix logic for clearing the IOMMU interrupt bits Date: Thu, 13 Jun 2013 11:34:09 -0500 Message-ID: <51B9F481.50204@amd.com> References: <1370840751-11277-1-git-send-email-suravee.suthikulpanit@amd.com> <51B5CCF002000078000DC9A5@nat28.tlf.novell.com> <20130610121855.GE8802@ocelot.phlegethon.org> <51B5E58802000078000DCA7E@nat28.tlf.novell.com> <51B6E40A02000078000DCF6C@nat28.tlf<51B6E40A02000078000DCF6C@nat28.tlf.novell.com> <51B7ACB5.7070805@amd.com> <51B8303302000078000DD6B6@nat28.tlf.novell.com> <51B8F814.70202@amd.com> <51B923F1.7000802@amd.com> <51BA082C02000078000DE0C0@nat28.tlf.novell.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <51BA082C02000078000DE0C0@nat28.tlf.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Jan Beulich Cc: Tim Deegan , xen-devel@lists.xen.org, Jacob Shin , Sherry Hurwitz List-Id: xen-devel@lists.xenproject.org On 6/13/2013 10:58 AM, Jan Beulich wrote: >>>> On 13.06.13 at 03:44, Suravee Suthikulpanit wrote: >> The following commit broke the IOMMU MSI interrupt: >> >> 2012-11-28 899110e3f6d2a191638e8b50a981c551eeec49e6 AMD IOMMU: >> include IOMMU interrupt information in 'M' debug key output >> (http://xenbits.xen.org/gitweb/?p=xen.git;a=commit;h=899110e3f6d2a191638e8b5 >> 0a981c551eeec49e6) > Having gone over the changes again, this still looks pretty innocent/ > mechanical to me - I can't see what may have got broken. > Considering that this is the change adding respective information to > 'M' output - what does 'M' show for the IOMMU entry/entries? > > Jan > > Basically, the only different is this line that only appears in the "Bad" version. (XEN) MSI 56 vec=28 fixed edge deassert phys cpu dest=00000001 mask=0/0/1 "xl debug-key i" also show the following information (XEN) IRQ: 56 affinity:1 vec:28 type=AMD-IOMMU-MSI status=00000000 mapped, unbound Not sure what "status=0" means. Before: (Good) (XEN) MSI information: (XEN) MSI 57 vec=c0 lowest edge assert log lowest dest=00000001 mask=0/1/1 (XEN) MSI 58 vec=c8 lowest edge assert log lowest dest=00000001 mask=0/1/1 (XEN) MSI 59 vec=d0 lowest edge assert log lowest dest=00000001 mask=0/1/1 (XEN) MSI 60 vec=d8 lowest edge assert log lowest dest=00000001 mask=0/1/1 (XEN) MSI 61 vec=29 lowest edge assert log lowest dest=00000001 mask=0/1/1 (XEN) MSI-X 62 vec=31 lowest edge assert log lowest dest=00000001 mask=1/0/0 (XEN) MSI-X 63 vec=39 lowest edge assert log lowest dest=00000001 mask=1/0/0 (XEN) MSI-X 64 vec=41 lowest edge assert log lowest dest=00000001 mask=1/0/0 (XEN) MSI-X 65 vec=49 lowest edge assert log lowest dest=00000001 mask=1/0/0 (XEN) MSI-X 66 vec=51 lowest edge assert log lowest dest=00000001 mask=1/0/0 (XEN) MSI-X 67 vec=59 lowest edge assert log lowest dest=00000001 mask=1/0/0 (XEN) MSI 68 vec=69 lowest edge assert log lowest dest=00000001 mask=0/1/1 (XEN) MSI-X 69 vec=79 lowest edge assert log lowest dest=00000003 mask=1/1/1 (XEN) MSI-X 70 vec=81 lowest edge assert log lowest dest=00000003 mask=1/1/1 (XEN) MSI-X 71 vec=89 lowest edge assert log lowest dest=00000003 mask=1/1/1 (XEN) MSI-X 72 vec=99 lowest edge assert log lowest dest=00000001 mask=1/0/0 (XEN) MSI-X 73 vec=a1 lowest edge assert log lowest dest=00000002 mask=1/0/0 (XEN) MSI-X 74 vec=a9 lowest edge assert log lowest dest=00000001 mask=1/0/0 (XEN) MSI 75 vec=b9 lowest edge assert log lowest dest=00000001 mask=0/1/1 (XEN) MSI 76 vec=c1 lowest edge assert log lowest dest=00000001 mask=0/1/1 After: (Bad) (XEN) MSI information: (XEN) MSI 56 vec=28 fixed edge deassert phys cpu dest=00000001 mask=0/0/1 (XEN) MSI 57 vec=c0 lowest edge assert log lowest dest=00000001 mask=0/1/1 (XEN) MSI 58 vec=c8 lowest edge assert log lowest dest=00000001 mask=0/1/1 (XEN) MSI 59 vec=d0 lowest edge assert log lowest dest=00000001 mask=0/1/1 (XEN) MSI 60 vec=d8 lowest edge assert log lowest dest=00000001 mask=0/1/1 (XEN) MSI 61 vec=29 lowest edge assert log lowest dest=00000001 mask=0/1/1 (XEN) MSI-X 62 vec=31 lowest edge assert log lowest dest=00000001 mask=1/0/0 (XEN) MSI-X 63 vec=39 lowest edge assert log lowest dest=00000001 mask=1/0/0 (XEN) MSI-X 64 vec=41 lowest edge assert log lowest dest=00000001 mask=1/0/0 (XEN) MSI-X 65 vec=49 lowest edge assert log lowest dest=00000001 mask=1/0/0 (XEN) MSI-X 66 vec=51 lowest edge assert log lowest dest=00000001 mask=1/0/0 (XEN) MSI-X 67 vec=59 lowest edge assert log lowest dest=00000001 mask=1/0/0 (XEN) MSI 68 vec=71 lowest edge assert log lowest dest=00000001 mask=0/1/1 (XEN) MSI-X 69 vec=79 lowest edge assert log lowest dest=00000003 mask=1/1/1 (XEN) MSI-X 70 vec=81 lowest edge assert log lowest dest=00000003 mask=1/1/1 (XEN) MSI-X 71 vec=89 lowest edge assert log lowest dest=00000003 mask=1/1/1 (XEN) MSI-X 72 vec=99 lowest edge assert log lowest dest=00000001 mask=1/0/0 (XEN) MSI-X 73 vec=a1 lowest edge assert log lowest dest=00000002 mask=1/0/0 (XEN) MSI-X 74 vec=a9 lowest edge assert log lowest dest=00000001 mask=1/0/0 (XEN) MSI 75 vec=b9 lowest edge assert log lowest dest=00000001 mask=0/1/1 (XEN) MSI 76 vec=c1 lowest edge assert log lowest dest=00000001 mask=0/1/1 Suravee