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From: Boris Ostrovsky <boris.ostrovsky@oracle.com>
To: Suravee Suthikulanit <suravee.suthikulpanit@amd.com>
Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>,
	"haitao.shan@intel.com" <haitao.shan@intel.com>,
	"Shin, Jacob" <Jacob.Shin@amd.com>,
	"dietmar.hahn@ts.fujitsu.com" <dietmar.hahn@ts.fujitsu.com>,
	"xen-devel@lists.xen.org" <xen-devel@lists.xen.org>,
	"jun.nakajima@intel.com" <jun.nakajima@intel.com>
Subject: Re: [PATCH 3/8] x86/AMD: Read VPMU MSRs from context when it is not loaded into HW
Date: Wed, 19 Jun 2013 19:32:38 -0400	[thread overview]
Message-ID: <51C23F96.5080509@oracle.com> (raw)
In-Reply-To: <51C23713.6020301@amd.com>


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On 06/19/2013 06:56 PM, Suravee Suthikulanit wrote:
> On 4/16/2013 1:36 PM, Konrad Rzeszutek Wilk wrote:
>> On Tue, Apr 16, 2013 at 12:12:16PM -0500, Jacob Shin wrote:
>> > On Tue, Apr 16, 2013 at 11:41:51AM -0400, Konrad Rzeszutek Wilk wrote:
>> > > On Thu, Apr 11, 2013 at 02:34:47PM -0400, Boris Ostrovsky wrote:
>> > > > On 04/11/2013 02:26 PM, Suravee Suthikulpanit wrote:
>> > > > >Boris,
>> > > > >
>> > > > >I tried booting the guest HVM after the patch, I still see PERF
>> > > > >only working in Software mode only.  I'll look more into this.
>> > > >
>> > > > You may need to declare proper CPUID bits in the config file. On
>> > > > fam15h I have
>> > > >
>> > > > cpuid=['0x80000001:ecx=00000001101000011000101111110011']
>> > >
>> > > Would it be possible to write somewhere this magic incantention?
>> > >
>> > > Perhaps in the xl.cfg.pod.5 ?
>> > >
>> > > (This of course being a different patch).
>> > >
>> >
>> > Well, maybe we should turn it on by default?
>> >
>> > http://lists.xen.org/archives/html/xen-devel/2013-04/msg01028.html:
>> >
>> > diff --git a/tools/libxc/xc_cpuid_x86.c b/tools/libxc/xc_cpuid_x86.c
>> > index 17efc0f..c269468 100644
>> > --- a/tools/libxc/xc_cpuid_x86.c
>> > +++ b/tools/libxc/xc_cpuid_x86.c
>> > @@ -112,6 +112,7 @@ static void amd_xc_cpuid_policy(
>> >                       bitmaskof(X86_FEATURE_XOP) |
>> >                       bitmaskof(X86_FEATURE_FMA4) |
>> >                       bitmaskof(X86_FEATURE_TBM) |
>> > +                    bitmaskof(X86_FEATURE_PERFCTR_CORE) |
>> >                       bitmaskof(X86_FEATURE_LWP));
>> > regs[3] &= (0x0183f3ff | /* features shared with 0x00000001:EDX */
>> >                       (is_pae ? bitmaskof(X86_FEATURE_NX) : 0) |
>> >
>> > Or maybe not since vpmu is not on by default .. ?
>>
>> I would say not yet. As the vpmu=1 (at least on Intel) has some issues.
>> Until that is fixed and vpmu=1 is by default lets leave it as so.
>>
>> >
>>
> Konrad, Boris:
> I would like to ask you to reconsider accepting this patch for 4.3.

I think it missed 4.3 anyway.

>
> This bit and vpmu=1 are independent of each other.  Without vpmu=1 option, PERF in HVM guest
> will not work regardless of this bit. So, it should be safe to always setting this bit.
> However, if user set vpmu=1 and not _manually_ setting this bit, the PERF logic will
> break and users will be getting incorrect result.


Why would you need to set this bit by hand in addition to having the 
patch? With this patch I see ecx=0x00a18bf3. I.e. bit 23 is set, as 
expected.

-boris


>
> The bit is currently used in the Linux PERF logic for all family15h to
> tell that there are 6 counters instead of 4 counters (when bit the is not set).
> Also, it will be using a different set of event constrain. The current Linux PERF
> core PMU logic assume that this bit will always be available.
>
> Suravee
>   
>
>
>
>
>
>
> _______________________________________________
> Xen-devel mailing list
> Xen-devel@lists.xen.org
> http://lists.xen.org/xen-devel


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  reply	other threads:[~2013-06-19 23:32 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-04-09 17:26 [PATCH 0/8] Various VPMU patches Boris Ostrovsky
2013-04-09 17:26 ` [PATCH 1/8] x86/AMD: Allow more fine-grained control of VMCB MSR Permission Map Boris Ostrovsky
2013-04-09 17:26 ` [PATCH 2/8] x86/AMD: Do not intercept access to performance counters MSRs Boris Ostrovsky
2013-04-10 13:25   ` Jan Beulich
2013-04-09 17:26 ` [PATCH 3/8] x86/AMD: Read VPMU MSRs from context when it is not loaded into HW Boris Ostrovsky
2013-04-11 18:26   ` Suravee Suthikulpanit
2013-04-11 18:34     ` Boris Ostrovsky
2013-04-11 19:30       ` Suravee Suthikulpanit
2013-04-16 15:41       ` Konrad Rzeszutek Wilk
2013-04-16 17:12         ` Jacob Shin
2013-04-16 18:36           ` Konrad Rzeszutek Wilk
2013-06-19 22:56             ` Suravee Suthikulanit
2013-06-19 23:32               ` Boris Ostrovsky [this message]
2013-06-19 23:53                 ` Boris Ostrovsky
2013-04-09 17:26 ` [PATCH 4/8] x86/AMD: Stop counters on VPMU save Boris Ostrovsky
2013-04-09 17:26 ` [PATCH 5/8] x86/VPMU: Add Haswell support Boris Ostrovsky
2013-04-09 17:26 ` [PATCH 6/8] x86/VPMU: Factor out VPMU common code Boris Ostrovsky
2013-04-10 16:03   ` Nakajima, Jun
2013-04-09 17:26 ` [PATCH 7/8] x86/VPMU: Save/restore VPMU only when necessary Boris Ostrovsky
2013-04-10  8:57   ` Dietmar Hahn
2013-04-10 12:53     ` Boris Ostrovsky
2013-04-09 17:26 ` [PATCH 8/8] x86/AMD: Clean up context_update() in AMD VPMU code Boris Ostrovsky
2013-04-11 19:48   ` Suravee Suthikulpanit
2013-04-11 20:42     ` Boris Ostrovsky
2013-04-10  8:57 ` [PATCH 0/8] Various VPMU patches Dietmar Hahn
2013-04-10 18:49 ` Suravee Suthikulanit
2013-04-10 19:10   ` Boris Ostrovsky

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